公开(公告)号：US09209966B1

公开(公告)日：2015-12-08

申请号：US14687766

申请日：2015-04-15

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Jared L. Zerbe ,  Myeong-Jae Park

IPC: H03D3/24 ,  H04L7/033 ,  H04L7/00 ,  H04L25/03 ,  H03L7/091

CPC classification number: H04L7/0331 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L25/03146 ,  H04L2025/03445

Abstract: This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.

公开(公告)号：US09036764B1

公开(公告)日：2015-05-19

申请号：US14050202

申请日：2013-10-09

Applicant: Rambus Inc.

Inventor： Masum Hossain ,  Jared L. Zerbe ,  Myeong-Jae Park

IPC: H04L7/00 ,  H03D3/24 ,  H04L7/033

CPC classification number: H04L7/0331 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L25/03146 ,  H04L2025/03445

Abstract: This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.

Abstract translation: 本公开提供了具有具有两点调制的锁相环（PLL）的时钟恢复电路。 二进制相位误差信号控制可变频率振荡器（VFO）的反馈路径，而线性相位误差信号控制该反馈路径外的PLL。 使用超低延迟延迟路径注入线性相位误差信号。 当二进制相位误差信号设置PLL的锁定点时，线性相位误差路径在高频下占主导地位，并且有助于减少抖动抖动。 其他可选功能包括区域有效的混合相位检测器，其产生二进制和线性相位误差信号，使用PLL内的相位内插器来进一步平滑抖动抖动，针对特定数据转换的恢复时钟更新滤波，以及支持多 -PAM信令。