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1.发明授权Data processing system with fully interconnected system architecture (FISA) 失效具有完全互连系统架构（FISA）的数据处理系统公开(公告)号：US06553447B1
公开(公告)日：2003-04-22
申请号：US09437194
申请日：1999-11-09
IPC分类号： G06F1300
CPC分类号： G06F13/4273
摘要： A Fully Interconnected System Architecture (FISA) for an improved data processing system. The data processing system topology has a processor chip and external components to the processor chip, such as memory and input/output (I/O) and other processor chips. The processor chip is interconnected to the external components via a point-to-point bus topology controlled by an intra-chip integrated, distributed switch (IDS) controller. The IDS controller provides the chip with the functionality to provide a single bus to each external component and provides an overall total bandwidth greater than traditional topologies while reducing latencies between the processor and the external components. The design of the processor chip with the intra-chip IDS controller provides a pseudo “distributed switch” which may separately access distributed external components, such as memory and I/Os, etc.
摘要翻译： 完全互连的系统架构（FISA），用于改进的数据处理系统。 数据处理系统拓扑具有处理器芯片和处理器芯片的外部组件，例如存储器和输入/输出（I / O）等处理器芯片。 处理器芯片通过由片上集成分布式交换机（IDS）控制器控制的点对点总线拓扑与外部组件互连。 IDS控制器为芯片提供功能，为每个外部组件提供单个总线，并提供比传统拓扑更大的总体带宽，同时减少处理器和外部组件之间的延迟。 具有片内IDS控制器的处理器芯片的设计提供了一种伪“分布式交换机”，可以分别访问分布式的外部组件，如存储器和I / O等。
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2.发明授权Multiprocessor system with a high performance integrated distributed switch (IDS) controller 失效具有高性能集成分布式交换机（IDS）控制器的多处理器系统公开(公告)号：US06415424B1
公开(公告)日：2002-07-02
申请号：US09437195
申请日：1999-11-09
IPC分类号： G06F1750
CPC分类号： G06F15/7832
摘要： A data processing system having a modified processor chip and external components to the processor chip. The processor chip is interconnected to the external components via point-to-point bus connections controlled by an integrated distributed switch (IDS) controller. The IDS controller is placed, during chip design, in the upper layer metals of the processor chip. When the data processing system is a multi-chip multiprocessor data processing system, the IDS controller operates to provide a pseudo switching effect whereby the processor is directly connected to each external component. The IDS controller permits the processor to have greater communication bandwidth and reduced latencies with the external components. It also allows for a connection to distributed external components such as memory and I/O, etc. with overall reduced system components.
摘要翻译： 一种数据处理系统，其具有修改的处理器芯片和处理器芯片的外部组件。 处理器芯片通过由集成分布式交换机（IDS）控制器控制的点对点总线连接与外部组件互连。 IDS控制器在芯片设计期间放置在处理器芯片的上层金属中。 当数据处理系统是多芯片多处理器数据处理系统时，IDS控制器操作以提供伪切换效果，由此处理器直接连接到每个外部组件。 IDS控制器允许处理器具有更大的通信带宽和减少外部组件的延迟。 它还允许与分布式外部组件（如存储器和I / O等）连接，并具有整体减少的系统组件。
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公开(公告)号：US06598118B1
公开(公告)日：2003-07-22
申请号：US09364284
申请日：1999-07-30
IPC分类号： G60F1200
CPC分类号： G06F12/0864
摘要： A processor having a hashed and partitioned storage subsystem includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a cache subsystem including a plurality of caches that store data utilized by the execution unit. Each cache among the plurality of caches stores only data having associated addresses within a respective one of a plurality of subsets of an address space. In one preferred embodiment, the execution units of the processor include a number of load-store units (LSUs) that each process only instructions that access data having associated addresses within a respective one of the plurality of address subsets. The processor may further be incorporated within a data processing system having a number of interconnects and a number of sets of system memory hardware that each have affinity to a respective one of the plurality of address subsets.
摘要翻译： 具有散列和分区存储子系统的处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和包括存储由执行单元使用的数据的多个高速缓存的高速缓存子系统。 多个高速缓存中的每个高速缓存仅存储具有地址空间的多个子集中的相应地址内的相关地址的数据。 在一个优选实施例中，处理器的执行单元包括多个加载存储单元（LSU），每个加载存储单元仅处理访问在多个地址子集中的相应一个地址子集内具有相关联地址的数据的指令。 处理器还可以并入具有多个互连的数据处理系统和多个系统存储器硬件的集合，每个系统存储器硬件各自对多个地址子集中的相应一个具有亲和力。
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4.发明授权Method for providing high availability within a data processing system via a reconfigurable hashed storage subsystem 失效一种通过可重配置散列存储子系统在数据处理系统内提供高可用性的方法公开(公告)号：US06823471B1
公开(公告)日：2004-11-23
申请号：US09364281
申请日：1999-07-30
IPC分类号： G06F1100
CPC分类号： G06F11/20
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing a respective one of a plurality of data streams. If an error is detected in a particular hardware partition, the data stream assigned to that hardware partition is reassigned to another of the plurality of hardware partitions, thus preventing an error in one of the hardware partitions from resulting in a catastrophic failure.
摘要翻译： 处理器包括执行资源，数据存储和指令排序单元，其耦合到执行资源和数据存储器，其将数据存储器内的指令提供给执行资源。 执行资源，数据存储和指令排序单元中的至少一个由具有用于处理多个数据流中的相应一个的类似功能的多个硬件分区来实现。 如果在特定硬件分区中检测到错误，则分配给该硬件分区的数据流被重新分配给多个硬件分区中的另一个，从而防止其中一个硬件分区中的错误导致灾难性故障。
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5.发明授权Address dependent caching behavior within a data processing system having HSA (hashed storage architecture) 失效具有HSA（散列存储架构）的数据处理系统中的依赖于地址的缓存行为公开(公告)号：US06446165B1
公开(公告)日：2002-09-03
申请号：US09364287
申请日：1999-07-30
IPC分类号： G06F1300
CPC分类号： G06F12/0811
摘要： A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, each store only data having associated addresses within a respective one of a plurality of subsets of an address space and implement diverse caching behaviors. The diverse caching behaviors can include differing memory update policies, differing coherence protocols, differing prefetch behaviors, and differing cache line replacement policies.
摘要翻译： 处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和在同一级别的多个高速缓存。 存储由执行单元使用的数据的高速缓存仅存储具有地址空间的多个子集中的相应地址内的相关联地址的数据，并且实现多种缓存行为。 不同的缓存行为可以包括不同的内存更新策略，不同的一致性协议，不同的预取行为以及不同的缓存行替换策略。
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公开(公告)号：US6000014A
公开(公告)日：1999-12-07
申请号：US834490
申请日：1997-04-14
IPC分类号： G06F12/08
CPC分类号： G06F12/0864
摘要： A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. Program instructions are loaded in the processor for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes is then defined using a mapping function which operates on the encoded addresses, such that the program instructions may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The program instructions can modify the original addresses by setting a plurality of programmable fields. Application software may provide the program instructions, wherein congruence classes are programmed based on a particular procedure of the application software which is running on the processor, that might otherwise run with excessive "striding" of the cache. Alternatively, operating-system software may monitor allocation of memory blocks in the cache and provides the program instructions to modify the original addresses based on the allocation of the memory blocks, to lessen striding.
摘要翻译： 公开了一种在由计算机系统的处理器使用的高速缓存器中提供可编程一致等级的方法。 程序指令被加载到处理器中，用于修改存储器件中的存储器块的原始地址以产生编码的地址。 然后使用对编码地址进行操作的映射函数来定义多个高速缓存一致等级，使得程序指令可以用于任意地将给定的一个原始地址分配给高速缓存一致性类的特定一个。 程序指令可以通过设置多个可编程字段来修改原始地址。 应用软件可以提供程序指令，其中根据在处理器上运行的应用软件的特定过程对一致性类进行编程，否则可能以高速缓存的“跨步”运行。 或者，操作系统软件可以监视高速缓存中的存储器块的分配，并且提供程序指令以基于存储器块的分配来修改原始地址，以减少跨越。
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公开(公告)号：US5983322A
公开(公告)日：1999-11-09
申请号：US839560
申请日：1997-04-14
IPC分类号： G06F12/08
CPC分类号： G06F12/0864
摘要： A method of providing programmable congruence classes in a cache used by a processor of a computer system is disclosed. A logic unit is connected to the cache for modifying original addresses of memory blocks in a memory device to produce encoded addresses. A plurality of cache congruence classes are then defined using a mapping function which operates on the encoded addresses, such that the logic unit may be used to arbitrarily assign a given one of the original addresses to a particular one of the cache congruence classes. The logic unit can modify the original addresses by setting a plurality of programmable fields. The logic unit also can collect information on cache misses, and modify the original addresses in response to the cache miss information. In this manner, a procedure running on the processor and allocating memory blocks to the cache such that the original addresses, if applied to the mapping function, would result in striding of the cache, runs more efficiently by using the encoded addresses to result in less striding of the cache.
摘要翻译： 公开了一种在由计算机系统的处理器使用的高速缓存器中提供可编程一致等级的方法。 逻辑单元连接到高速缓存，用于修改存储器设备中的存储器块的原始地址以产生编码的地址。 然后使用对编码的地址进行操作的映射函数来定义多个高速缓存一致等级，使得逻辑单元可以用于任意地将给定的一个原始地址分配给高速缓存一致性类别中的特定一个。 逻辑单元可以通过设置多个可编程字段来修改原始地址。 逻辑单元还可以收集关于高速缓存未命中的信息，并且响应于缓存未命中信息修改原始地址。 以这种方式，在处理器上运行的过程并将存储器块分配给高速缓存，使得原始地址（如果应用于映射功能）将导致高速缓存的跨越，则通过使用编码的地址来更有效地运行以导致较少的 跨越缓存。
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8.发明授权Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction 失效为存储器访问指令散列目标地址，以便在执行之前确定哪个特定的加载/存储单元处理该指令公开(公告)号：US06658556B1
公开(公告)日：2003-12-02
申请号：US09364288
申请日：1999-07-30
IPC分类号： G06F1730
CPC分类号： G06F9/3885 , G06F9/3013 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/384 , G06F9/3891
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store units that each process only instructions that access data having associated addresses within a respective one of a plurality of subsets of an address space. The load-store units can have diverse hardware such that a maximum number of instructions that can be concurrently executed is different for different load-store units or such that some of the load-store units are restricted to executing certain classes of instructions.
摘要翻译： 处理器包括执行资源，数据存储和与数据存储器和执行资源耦合的指令排序单元，其将数据存储器内的指令提供给执行资源。 执行资源包括多个加载存储单元，每个加载存储单元仅处理在地址空间的多个子集中的相应一个子集内访问具有相关联地址的数据的指令。 加载存储单元可以具有不同的硬件，使得可以并发执行的最大数量的指令对于不同的加载存储单元是不同的，或者使得一些加载存储单元被限制为执行某些类别的指令。
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公开(公告)号：US06449691B1
公开(公告)日：2002-09-10
申请号：US09364285
申请日：1999-07-30
IPC分类号： G06F1300
CPC分类号： G06F12/0846 , G06F12/0607 , G06F12/0848 , G06F12/0864 , G06F12/0897
摘要： A processor includes at least one execution unit, an instruction sequencing unit coupled to the execution unit, and a plurality of caches at a same level. The caches, which store data utilized by the execution unit, have diverse cache hardware and each preferably store only data having associated addresses within a respective one of a plurality of subsets of an address space. The diverse cache hardware can include, for example, differing cache sizes, differing associativities, differing sectoring, and differing inclusivities.
摘要翻译： 处理器包括至少一个执行单元，耦合到执行单元的指令排序单元和在同一级别的多个高速缓存。 存储由执行单元使用的数据的高速缓存具有不同的高速缓存硬件，并且每个高速缓存优选仅存储具有地址空间的多个子集中的相应地址内的相关联的地址的数据。 不同的高速缓存硬件可以包括例如不同的高速缓存大小，不同的相关性，不同的扇区和不同的包容性。
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10.发明授权Processor assigning data to hardware partition based on selectable hash of data address 失效处理器根据数据地址的可选哈希分配数据到硬件分区公开(公告)号：US06470442B1
公开(公告)日：2002-10-22
申请号：US09364286
申请日：1999-07-30
IPC分类号： B06F1576
CPC分类号： G06F9/3891 , G06F9/3012 , G06F9/3013 , G06F9/3802 , G06F9/384 , G06F9/3885 , G06F15/7857
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the execution resources and the data storage, that supplies instructions within the data storage to the execution resources. At least one of the execution resources, the data storage, and the instruction sequencing unit is implemented with a plurality of hardware partitions of like function for processing data. The data processed by each hardware partition is assigned according to a selectable hash of addresses associated as with the data. In a preferred embodiment, the selectable hash can be altered dynamically during the operation of the processor, for example, in response to detection of an error or a load imbalance between the hardware partitions.
摘要翻译： 处理器包括执行资源，数据存储和指令排序单元，其耦合到执行资源和数据存储器，其将数据存储器内的指令提供给执行资源。 执行资源，数据存储和指令排序单元中的至少一个用多个用于处理数据的相同功能的硬件分区来实现。 由每个硬件分区处理的数据根据与数据相关联的地址的可选择的散列来分配。 在优选实施例中，可以在处理器的操作期间动态地改变可选择的散列，例如响应于硬件分区之间的错误或负载不平衡的检测。
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