公开(公告)号：US20180226480A1

公开(公告)日：2018-08-09

申请号：US15889507

申请日：2018-02-06

Applicant: ROHM CO., LTD.

Inventor： Hajime OKUDA ,  Adrian JOITA

IPC: H01L29/423 ,  H01L29/78 ,  H01L29/739 ,  H01L29/66 ,  H01L21/265 ,  H01L27/092

CPC classification number: H01L29/4236 ,  H01L21/26586 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/083 ,  H01L29/1095 ,  H01L29/407 ,  H01L29/42376 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a main surface at which a trench is formed, a gate insulating layer formed along a side wall of the trench, a gate electrode embedded in the trench with the gate insulating layer interposed therebetween and having an upper surface located below the main surface of the semiconductor layer, a second conductivity type region formed in a surface layer portion of the main surface of the semiconductor layer and facing the gate electrode with the gate insulating layer interposed therebetween, a first conductivity type region formed in a surface layer portion of the second conductivity type region and facing the gate electrode with the gate insulating layer interposed therebetween, and a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode.

公开(公告)号：US20240258208A1

公开(公告)日：2024-08-01

申请号：US18616483

申请日：2024-03-26

Applicant: ROHM CO., LTD.

Inventor： Hajime OKUDA ,  Adrian JOITA

IPC: H01L23/495 ,  H01L23/00 ,  H01L25/065

CPC classification number: H01L23/49527 ,  H01L23/49575 ,  H01L24/08 ,  H01L24/48 ,  H01L25/0652 ,  H01L2224/08145 ,  H01L2224/08245 ,  H01L2224/48132 ,  H01L2224/48177 ,  H01L2924/0665 ,  H01L2924/1306

Abstract: A semiconductor device includes a semiconductor chip including a first principal surface in which an element region is formed and a peripheral end surface surrounding the first principal surface and an inspection wiring formed along the peripheral end surface on a side of the first principal surface of the semiconductor chip and that surrounds the element region, and, the inspection wiring includes a plurality of internal wiring portions that are formed at a surficial portion of the first principal surface of the semiconductor chip and that are arrayed at a distance from each other along the peripheral end surface of the semiconductor chip and a extending wiring portion that is formed on the first principal surface of the semiconductor chip and that is provided between the internal wiring portions adjoining each other, and the internal wiring portion and the extending wiring portion are alternately arrayed along the peripheral end surface.

公开(公告)号：US20240105834A1

公开(公告)日：2024-03-28

申请号：US18466322

申请日：2023-09-13

Applicant: ROHM CO., LTD.

Inventor： Hajime OKUDA ,  Yoshinori FUKUDA ,  Adrian JOITA ,  Toru TAKUMA

IPC: H01L29/78 ,  H01L27/06 ,  H01L29/06 ,  H01L29/423

CPC classification number: H01L29/7813 ,  H01L27/0629 ,  H01L29/0607 ,  H01L29/42368 ,  H01L29/42376

Abstract: A semiconductor device includes: a semiconductor region of a first conductivity type having a main surface; a capacitor region of a second conductivity type formed in a surface layer portion of the main surface; and at least one trench structure including a trench formed in the main surface to penetrate the capacitor region, an insulating film covering a wall surface of the trench, and embedded electrodes embedded in the trench so as to form capacitive coupling with the capacitor region through the insulating film.

公开(公告)号：US20230102188A1

公开(公告)日：2023-03-30

申请号：US17902295

申请日：2022-09-02

Applicant: Rohm Co., Ltd.

Inventor： Toru Takuma ,  Adrian JOITA ,  Shuntaro TAKAHASHI

IPC: H03F1/52 ,  H03F3/217

Abstract: An overcurrent protection circuit includes: a first transistor and a second transistor configured to form an amplifier input stage that receives input of a detection signal according to a monitoring target current; and a third transistor configured to form an amplifier output stage that generates a current output signal according to a difference between the detection signal and a reference signal and causes the current output signal to be negatively fed back to the amplifier input stage, wherein the monitoring target current is limited based on the current output signal output from the third transistor.