公开(公告)号：US20240347441A1

公开(公告)日：2024-10-17

申请号：US18753858

申请日：2024-06-25

申请人： Texas Instruments Incorporated

发明人： Anindya Poddar ,  Ashok Surendra Prabhu ,  Edgar Dorotyao Balidoy ,  Hau Nguyen ,  Makoto Yoshino ,  MING LI

IPC分类号： H01L23/498 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H05K1/02

CPC分类号： H01L23/49861 ,  H01L21/4839 ,  H01L21/565 ,  H01L23/49844 ,  H01L24/48 ,  H05K1/0204 ,  H01L2224/48177 ,  H01L2224/48178 ,  H01L2224/48248 ,  H01L2224/48465 ,  H01L2924/1811 ,  H01L2924/182

摘要： A described example includes: a package substrate having a die pad with a die side surface and having an opposite backside surface, having leads arranged along two opposite sides and having die pad straps extending from two opposing ends of the die pad. The leads lie in a first plane, a portion of the die pad straps lie in a second plane that is spaced from the first plane and located closer to the die pad, and the die pad lies in a third plane that is spaced from and parallel to the second plane in a direction away from the first plane. A semiconductor die is mounted to the die side surface and mold compound covers the semiconductor die, a portion of the leads, and the die side surface of the die pad, and the backside surface of the die pad exposed from the mold compound.

公开(公告)号：US20240243039A1

公开(公告)日：2024-07-18

申请号：US18098560

申请日：2023-01-18

申请人： Advanced Semiconductor Engineering, Inc.

发明人： Ying-Chung CHEN

IPC分类号： H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/49 ,  H01L25/065

CPC分类号： H01L23/4952 ,  H01L21/4885 ,  H01L21/56 ,  H01L23/3185 ,  H01L23/49 ,  H01L24/05 ,  H01L24/29 ,  H01L24/32 ,  H01L24/43 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/04042 ,  H01L2224/05568 ,  H01L2224/29023 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/48179 ,  H01L2224/4903 ,  H01L2224/49107 ,  H01L2924/182

摘要： At least some embodiments of the present disclosure relate to an electronic structure. The package structure includes a lead frame, an electronic component, and a conductive wire physically and electrically connecting the electronic component to the lead frame. An elevation of a first end of the conductive wire is substantially equal to an elevation of a second end of the conductive wire.

公开(公告)号：US12027579B2

公开(公告)日：2024-07-02

申请号：US16480203

申请日：2018-01-25

申请人： ROHM CO., LTD.

发明人： Seigo Mori ,  Masatoshi Aketa

IPC分类号： H01L29/06 ,  H01L21/02 ,  H01L21/04 ,  H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L29/16 ,  H01L29/32 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L29/872 ,  H02M7/00 ,  H02M7/5387 ,  H02P27/06

CPC分类号： H01L29/0634 ,  H01L21/0223 ,  H01L21/02529 ,  H01L21/046 ,  H01L21/0485 ,  H01L21/049 ,  H01L23/3121 ,  H01L23/49562 ,  H01L24/48 ,  H01L29/0657 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/32 ,  H01L29/417 ,  H01L29/4236 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/66734 ,  H01L29/7811 ,  H01L29/7813 ,  H01L29/872 ,  H02M7/003 ,  H02M7/5387 ,  H01L21/02255 ,  H01L2224/48177 ,  H01L2924/10272 ,  H01L2924/12032 ,  H01L2924/13091 ,  H02P27/06

摘要： A semiconductor device includes a semiconductor layer of a first conductivity type having a main surface, a diode region of the first conductivity type formed in a surface layer portion of the main surface of the semiconductor layer, a carrier trapping region including crystal defects and formed along a peripheral edge of the diode region in the surface layer portion of the main surface of the semiconductor layer, and an anode electrode formed on the main surface of the semiconductor layer and forming a Schottky junction with the diode region.

公开(公告)号：US12027450B2

公开(公告)日：2024-07-02

申请号：US17596414

申请日：2020-06-25

申请人： ROHM CO., LTD.

发明人： Toshiro Tsuchiyama ,  Yasumasa Kasuya ,  Tatsuo Yamazaki

IPC分类号： H01L23/495 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49541 ,  H01L23/3107 ,  H01L23/49503 ,  H01L24/48 ,  H01L24/45 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48177

摘要： An electronic device includes: an electronic element having an element obverse surface and an element reverse surface spaced apart from each other in a first direction, the element obverse surface being provided with an obverse-surface electrode; a resin member having a resin reverse surface facing in a same direction as the element reverse surface, the resin member covering the electronic element; and an electrically conductive member supporting the electronic element and electrically connected to the electronic element. The electrically conductive member has a first exposed region, a second exposed region and a third exposed region each of which is exposed from the resin reverse surface. The resin member has a first resin side surface and a second resin side surface connected to each other and standing up from the resin reverse surface. As viewed in the first direction, the first exposed region is located at a corner portion where the first resin side surface and the second resin side surface are connected. As viewed in the first direction, the second exposed region is located side by side with the first exposed region in a second direction extending along the first resin side surface. The third exposed region is located between the first exposed region and the second exposed region in the second direction. As viewed in the first direction, the third exposed region has a larger area than each of the first exposed region and the second exposed region.

公开(公告)号：US20180182642A1

公开(公告)日：2018-06-28

申请号：US15848336

申请日：2017-12-20

申请人： TEXAS INSTRUMENTS INCORPORATED

发明人： Dolores Babaran MILO ,  Cherry Lyn Marquez ARANAS

IPC分类号： H01L21/48 ,  H01L23/495 ,  H01L23/31 ,  H01L23/00

CPC分类号： H01L21/4828 ,  H01L23/3121 ,  H01L23/49541 ,  H01L23/49548 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/48108 ,  H01L2224/48177 ,  H01L2224/4917 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/49177

摘要： A multi-level leadframe including three bonding levels and one exposed level. Each of the three bonding levels and the one exposed level is positioned in a different horizontal plane, with each bonding level providing a bonding site vertically positioned relative to the horizontal plane of the exposed level, with each bonding site coupled to a package lead at the exposed level. Bonding sites located at first and second bonding levels can be located in a common, outer row, along a common, vertical plane, and bonding sites located at a third bonding level can be located in a separate, inner row, along a separate vertical plane. A third level bonding site can be coupled to a first level bonding site with a multiple level electrical lead conductor that vertically spans a second bonding level. A two-step etch process from a single sheet conductor is provided to manufacture the multi-level leadframe.

公开(公告)号：US09911838B2

公开(公告)日：2018-03-06

申请号：US13662384

申请日：2012-10-26

申请人： Kyoung Wook Seok

发明人： Kyoung Wook Seok

IPC分类号： H01L29/66 ,  H01L29/739 ,  H01L29/08 ,  H01L23/495 ,  H01L23/00 ,  H01L29/417 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01F38/30

CPC分类号： H01L29/7395 ,  H01F38/30 ,  H01L23/495 ,  H01L23/49562 ,  H01L24/06 ,  H01L24/48 ,  H01L24/49 ,  H01L29/0696 ,  H01L29/0834 ,  H01L29/1095 ,  H01L29/41741 ,  H01L29/4238 ,  H01L29/66333 ,  H01L2224/04042 ,  H01L2224/0603 ,  H01L2224/0616 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/4813 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48265 ,  H01L2224/48472 ,  H01L2224/49096 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2224/49176 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/12036 ,  H01L2924/13055 ,  H01L2924/181 ,  H01L2924/19104 ,  H01L2924/19107 ,  H01L2924/00012 ,  H01L2924/00

摘要： An IGBT die structure includes an auxiliary P well region. A terminal, that is not connected to any other IGBT terminal, is coupled to the auxiliary P well region. To accelerate IGBT turn on, a current is injected into the terminal during the turn on time. The injected current causes charge carriers to be injected into the N drift layer of the IGBT, thereby reducing turn on time. To accelerate IGBT turn off, charge carriers are removed from the N drift layer by drawing current out of the terminal. To reduce VCE(SAT), current can also be injected into the terminal during IGBT on time. An IGBT assembly involves the IGBT die structure and an associated current injection/extraction circuit. As appropriate, the circuit injects or extracts current from the terminal depending on whether the IGBT is in a turn on time or is in a turn off time.

公开(公告)号：US20180047698A1

公开(公告)日：2018-02-15

申请号：US15792398

申请日：2017-10-24

申请人： ROHM CO., LTD.

发明人： Mamoru YAMAGAMI ,  Kenji FUJII

IPC分类号： H01L23/00 ,  H01L23/495 ,  H01L23/31 ,  H01L23/525 ,  H01L23/532

CPC分类号： H01L24/49 ,  H01L23/3107 ,  H01L23/49524 ,  H01L23/49548 ,  H01L23/525 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/36 ,  H01L24/37 ,  H01L24/40 ,  H01L24/41 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/02375 ,  H01L2224/0346 ,  H01L2224/0347 ,  H01L2224/0391 ,  H01L2224/03914 ,  H01L2224/0401 ,  H01L2224/04034 ,  H01L2224/04042 ,  H01L2224/05008 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05026 ,  H01L2224/05147 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05557 ,  H01L2224/05567 ,  H01L2224/05571 ,  H01L2224/05583 ,  H01L2224/05599 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/08245 ,  H01L2224/13024 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13582 ,  H01L2224/13655 ,  H01L2224/13664 ,  H01L2224/1411 ,  H01L2224/16245 ,  H01L2224/37147 ,  H01L2224/40245 ,  H01L2224/40247 ,  H01L2224/40479 ,  H01L2224/40491 ,  H01L2224/40499 ,  H01L2224/40993 ,  H01L2224/4112 ,  H01L2224/45015 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/48824 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/4912 ,  H01L2224/49177 ,  H01L2224/73221 ,  H01L2224/8485 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/20754 ,  H01L2924/351 ,  H01L2924/00 ,  H01L2924/2075 ,  H01L2924/20757 ,  H01L2924/20756 ,  H01L2924/20758 ,  H01L2924/20759 ,  H01L2924/2076 ,  H01L2924/20755 ,  H01L2924/014 ,  H01L2224/051

摘要： An inventive semiconductor device includes: a semiconductor chip including an integrated circuit; a plurality of electrode pads provided on the semiconductor chip and connected to the integrated circuit; a rewiring to which the electrode pads are electrically connected together, the rewiring being exposed on an outermost surface of the semiconductor chip and having an exposed surface area greater than the total area of the electrode pads; and a resin package which seals the semiconductor chip.

公开(公告)号：US09887668B2

公开(公告)日：2018-02-06

申请号：US15259995

申请日：2016-09-08

申请人： Skyworks Solutions, Inc.

发明人： Peter J. Zampardi, Jr. ,  Hsiang-Chih Sun ,  Sandra Louise Petty-Weeks ,  Guohao Zhang ,  Hardik Bhupendra Modi

IPC分类号： H03F3/14 ,  H03F1/02 ,  H03F3/19 ,  H03F3/21 ,  H03F3/213 ,  H03F3/195 ,  H03F3/24 ,  H01L23/552 ,  H01L23/66 ,  H01L23/00 ,  H01L29/36 ,  H01L29/66 ,  H01L29/737 ,  H01L29/812 ,  H01L29/08 ,  H01L29/205 ,  H01L21/8252 ,  H01L27/06 ,  H01L23/498 ,  H01L23/50 ,  H03F3/60 ,  H01L29/20 ,  H01L23/48 ,  H01L21/48 ,  H01L21/56 ,  H01L21/78 ,  H01L21/8249 ,  H01L21/66 ,  H01L23/31 ,  H01L21/768 ,  H03F3/187 ,  H03F3/347 ,  H03F1/56 ,  H01L29/8605 ,  H01L27/092 ,  H03F3/45 ,  H01L29/06 ,  H01L29/10

CPC分类号： H03F1/0205 ,  H01L21/485 ,  H01L21/4853 ,  H01L21/4864 ,  H01L21/565 ,  H01L21/76898 ,  H01L21/78 ,  H01L21/8249 ,  H01L21/8252 ,  H01L22/14 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49811 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/49844 ,  H01L23/49861 ,  H01L23/49866 ,  H01L23/49894 ,  H01L23/50 ,  H01L23/522 ,  H01L23/552 ,  H01L23/66 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L24/97 ,  H01L27/0605 ,  H01L27/0623 ,  H01L27/092 ,  H01L29/0684 ,  H01L29/0821 ,  H01L29/0826 ,  H01L29/1004 ,  H01L29/20 ,  H01L29/205 ,  H01L29/36 ,  H01L29/66242 ,  H01L29/66863 ,  H01L29/737 ,  H01L29/7371 ,  H01L29/812 ,  H01L29/8605 ,  H01L2223/6611 ,  H01L2223/6616 ,  H01L2223/6644 ,  H01L2223/665 ,  H01L2223/6655 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/45015 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48177 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/48611 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48655 ,  H01L2224/48664 ,  H01L2224/48811 ,  H01L2224/48816 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/48855 ,  H01L2224/48864 ,  H01L2224/4903 ,  H01L2224/49111 ,  H01L2224/49176 ,  H01L2224/85205 ,  H01L2224/85207 ,  H01L2224/85411 ,  H01L2224/85416 ,  H01L2224/85444 ,  H01L2224/85455 ,  H01L2224/85464 ,  H01L2924/00011 ,  H01L2924/10253 ,  H01L2924/10329 ,  H01L2924/12033 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13051 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/1421 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/3011 ,  H01L2924/30111 ,  H01L2924/3025 ,  H03F1/565 ,  H03F3/187 ,  H03F3/19 ,  H03F3/195 ,  H03F3/21 ,  H03F3/213 ,  H03F3/245 ,  H03F3/347 ,  H03F3/45 ,  H03F3/60 ,  H03F2200/387 ,  H03F2200/451 ,  H03F2200/48 ,  H03F2200/555 ,  H01L2924/00 ,  H01L2924/00014

摘要： One aspect of this disclosure is a power amplifier module that includes a power amplifier configured to amplify a radio frequency (RF) signal and an RF transmission line electrically coupled to an output of the power amplifier. The power amplifier includes a heterojunction bipolar transistor and a p-type field effect transistor, in which a semiconductor portion of the p-type field effect transistor corresponds to a channel includes the same type of semiconductor material as a collector layer of the heterojunction bipolar transistor. The RF transmission line includes a nickel layer with a thickness that is less than 0.5 um, a conductive layer under the nickel layer, a palladium layer over the nickel layer, and a gold layer over the palladium layer. Other embodiments of the module are provided along with related methods and components thereof.

公开(公告)号：US20170287817A1

公开(公告)日：2017-10-05

申请号：US15629243

申请日：2017-06-21

申请人： ROHM CO., LTD.

发明人： Akihiro KOGA ,  Taro NISHIOKA

IPC分类号： H01L23/495 ,  H01L23/31 ,  H01L23/29 ,  H01L23/00

CPC分类号： H01L23/49548 ,  H01L23/293 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49 ,  H01L23/49503 ,  H01L23/4952 ,  H01L23/49541 ,  H01L24/32 ,  H01L24/42 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/1715 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2924/00012 ,  H01L2924/00

摘要： A semiconductor device is disclosed. The semiconductor device has a semiconductor chip, an island having an upper surface to which the semiconductor chip is bonded, a lead disposed around the island, a bonding wire extended between the surface of the semiconductor chip and the upper surface of the lead, and a resin package sealing the semiconductor chip, the island, the lead, and the bonding wire, while the lower surface of the island and the lower surface of the lead are exposed on the rear surface of the resin package, and the lead is provided with a recess concaved from the lower surface side and opened on a side surface thereof.

公开(公告)号：US20170250124A1

公开(公告)日：2017-08-31

申请号：US15252915

申请日：2016-08-31

申请人： KABUSHIKI KAISHA TOSHIBA

发明人： Naohisa OKUMURA ,  Yasuhisa SHINTOKU ,  Tetsuya KUROSAWA ,  Hiroaki KISHI

IPC分类号： H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/31

CPC分类号： H01L23/49503 ,  H01L21/4842 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49537 ,  H01L23/49541 ,  H01L23/49568 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L24/97 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48177 ,  H01L2224/48247 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/1033 ,  H01L2924/1306 ,  H01L2924/17747 ,  H01L2924/00014 ,  H01L2924/00

摘要： A semiconductor device that includes a first die pad, an adhesive, and a second die pad fixed to the top surface of the first die pad via the adhesive. The second die pad includes a body portion and a protrusion portion provided on a side surface of the body portion. A semiconductor chip is fixed to a top surface of the second die pad, and a lead is electrically connected to the semiconductor chip. The semiconductor device further includes a package material that covers the first die pad, the second die pad, the semiconductor chip, and the lead. The first die pad is substantially as thick as the lead.