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公开(公告)号:US20240153944A1
公开(公告)日:2024-05-09
申请号:US18414478
申请日:2024-01-17
Applicant: ROHM CO., LTD.
Inventor: Yuji OSUMI , Hajime OKUDA
IPC: H01L27/02 , H01L29/06 , H01L29/423 , H01L29/866
CPC classification number: H01L27/0255 , H01L29/0615 , H01L29/0696 , H01L29/4236 , H01L29/866
Abstract: The semiconductor device includes a chip which has a main surface, a diode region which is arranged in the main surface, trench structures which are formed in the main surface at an interval in the diode region, the trench structures each having an electrode structure including an upper electrode and a lower electrode which are embedded in a trench across an insulator in an up/down direction, and a diode which has a pn-junction portion that is formed in a surface layer portion of the main surface at a region between the trench structures.
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公开(公告)号:US20240097008A1
公开(公告)日:2024-03-21
申请号:US18462728
申请日:2023-09-07
Applicant: ROHM CO., LTD.
Inventor: Kazuhiro TAMURA , Naoki IZUMI , Hajime OKUDA
CPC classification number: H01L29/66681 , H01L29/086 , H01L29/0878 , H01L29/7824
Abstract: A semiconductor device includes: an n-type semiconductor layer; a p-type drift region formed in a surface layer of the n-type semiconductor layer; an n-type body region formed in the surface layer of the n-type semiconductor layer so as to be spaced apart from or adjacent to the p-type drift region; a p-type drain region formed in a surface layer of the p-type drift region; a p-type source region formed in a surface layer of the n-type body region; a gate insulating film formed over a surface of the n-type semiconductor layer so as to straddle the p-type drift region and the n-type body region; a gate electrode formed over the gate insulating film; and an n-type region formed in the surface layer of the p-type drift region and arranged between a side edge of the p-type drift region near the n-type body region and the p-type drain region.
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公开(公告)号:US20180226480A1
公开(公告)日:2018-08-09
申请号:US15889507
申请日:2018-02-06
Applicant: ROHM CO., LTD.
Inventor: Hajime OKUDA , Adrian JOITA
IPC: H01L29/423 , H01L29/78 , H01L29/739 , H01L29/66 , H01L21/265 , H01L27/092
CPC classification number: H01L29/4236 , H01L21/26586 , H01L27/092 , H01L27/0922 , H01L29/083 , H01L29/1095 , H01L29/407 , H01L29/42376 , H01L29/66348 , H01L29/66734 , H01L29/7397 , H01L29/7813
Abstract: A semiconductor device includes a semiconductor layer of a first conductivity type having a main surface at which a trench is formed, a gate insulating layer formed along a side wall of the trench, a gate electrode embedded in the trench with the gate insulating layer interposed therebetween and having an upper surface located below the main surface of the semiconductor layer, a second conductivity type region formed in a surface layer portion of the main surface of the semiconductor layer and facing the gate electrode with the gate insulating layer interposed therebetween, a first conductivity type region formed in a surface layer portion of the second conductivity type region and facing the gate electrode with the gate insulating layer interposed therebetween, and a side wall insulating layer covering the side wall of the trench in a recessed portion defined by the side wall of the trench and the upper surface of the gate electrode.
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公开(公告)号:US20240128169A1
公开(公告)日:2024-04-18
申请号:US18533721
申请日:2023-12-08
Applicant: ROHM CO., LTD.
Inventor: Hajime OKUDA , Yuto NISHIYAMA , Toru TAKUMA
IPC: H01L23/495 , H01L23/31
CPC classification number: H01L23/49568 , H01L23/3135 , H01L23/4952 , H01L23/49562 , H01L23/49575
Abstract: A semiconductor device is configured to increase energy absorbed by an active clamp. The semiconductor device comprises a semiconductor element, a sealing resin, and a coating member. The semiconductor element includes a first electrode. The sealing resin covers the semiconductor element. The coating member is interposed between the first electrode and the sealing resin. The coating member contains a material with higher thermal conductivity than the sealing resin.
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公开(公告)号:US20240014812A1
公开(公告)日:2024-01-11
申请号:US18471842
申请日:2023-09-21
Applicant: ROHM CO., LTD.
Inventor: Yoshinori FUKUDA , Hajime OKUDA , Yuji OSUMI
IPC: H03K17/08
CPC classification number: H03K17/08 , H01L29/0696
Abstract: A semiconductor device includes a main transistor which includes a first system transistor generating a first system current and a second system transistor generating a second system current independently of the first system transistor and which generates an output current including the first system current and the second system current, a first system monitor transistor which generates a first system monitor current that corresponds to the first system current, and a second system monitor transistor which generates a second system monitor current that corresponds to the second system current.
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公开(公告)号:US20190115290A1
公开(公告)日:2019-04-18
申请号:US16156845
申请日:2018-10-10
Applicant: ROHM CO., LTD.
Inventor: Hajime OKUDA , Yoshinori FUKUDA
IPC: H01L23/495 , H01L23/00
CPC classification number: H01L23/49558 , H01L21/76 , H01L21/76224 , H01L23/49513 , H01L23/4952 , H01L23/49524 , H01L23/49562 , H01L23/562 , H01L2224/0603 , H01L2224/45014 , H01L2224/48247 , H01L2224/48464 , H01L2224/4903 , H01L2224/49171 , H01L2924/181 , H01L2924/19107 , H01L2924/00012
Abstract: A semiconductor device includes a semiconductor layer that has a main surface including a defined region defined by a trench, a trench insulation layer formed in the trench, a field insulation layer that covers the defined region away from the trench, and a bridge insulation layer that is formed in a region between the trench and the field insulation layer in the defined region and that is connected to the trench insulation layer and to the field insulation layer.
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公开(公告)号:US20240213245A1
公开(公告)日:2024-06-27
申请号:US18544458
申请日:2023-12-19
Applicant: ROHM CO., LTD.
Inventor: Yoshinori FUKUDA , Hajime OKUDA , Keiji YAMAMOTO
IPC: H01L27/092 , H01L29/78
CPC classification number: H01L27/092 , H01L29/7813
Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor chip having an element main surface; a first element disposed on the element main surface; a second element disposed on the element main surface and separated from the first element; and a third element disposed on the element main surface and separated from the first element and the second element. The first element includes a DTI structure as a part of an element structure. The second element includes an STI structure. The third element includes a LOCOS structure.
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公开(公告)号:US20230326786A1
公开(公告)日:2023-10-12
申请号:US18022746
申请日:2021-09-16
Applicant: ROHM CO., LTD.
Inventor: Hajime OKUDA , Yuji OSUMI
IPC: H01L21/762 , H01L27/092 , H01L29/66 , H01L29/78 , H01L29/417 , H01L21/8238
CPC classification number: H01L21/76232 , H01L27/0922 , H01L29/66734 , H01L29/7813 , H01L29/41775 , H01L21/823878
Abstract: A semiconductor device includes a semiconductor chip that has a main surface, and a field insulating film that partially covers the main surface and has an insulating side wall in which an inclined angle made with the main surface is not less than 20° and not more than 40°.
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公开(公告)号:US20210344341A1
公开(公告)日:2021-11-04
申请号:US17245635
申请日:2021-04-30
Applicant: ROHM CO., LTD.
Inventor: Hajime OKUDA , Yoshinori FUKUDA
IPC: H03K17/687 , H01L29/78 , H01L29/06
Abstract: A semiconductor device includes a semiconductor chip, and an n-system gate divided transistor, where the “n” is not less than 2, that includes n-number of system transistors formed in the semiconductor chip such as to be individually controlled and that is configured such as to generate a single output signal by selective controls of the n-number of system transistors.
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公开(公告)号:US20200312975A1
公开(公告)日:2020-10-01
申请号:US16831791
申请日:2020-03-26
Applicant: ROHM CO., LTD.
Inventor: Yoshinori FUKUDA , Hajime OKUDA , Yuji OSUMI
IPC: H01L29/49 , H01L29/861 , G05F1/46
Abstract: A semiconductor device includes a substrate having a main surface, and a temperature-sensitive diode structure having a trench formed in the main surface, a polysilicon layer embedded in the trench, a p-type anode region formed in the polysilicon layer, and an n-type cathode region formed in the polysilicon layer.
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