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    Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability
    2.
    发明授权
    Optimizing long-path and short-path timing and accounting for manufacturing and operating condition variability 有权
    优化长途径和短路时间，并对制造和运行状况变化进行考虑

    公开(公告)号：US07290232B1

    公开(公告)日：2007-10-30

    申请号：US11002976

    申请日：2004-12-01

    申请人： Ryan Fung ,  Vaughn Betz

    发明人： Ryan Fung ,  Vaughn Betz

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： Logic designs are optimized to satisfy long-path and short-path timing constraints for multiple process/operating condition corners. A path-based compilation phase determines an implementation for logic design paths, in part, by monitoring a set of paths that are important from a timing perspective and evaluating the timing performance of the set of monitored paths at one or more timing corners. A timing-analysis-based compilation phase determines transformations for converting sets of timing values from one timing corner to another timing corner. The compilation phase transforms timing delay values from one timing corner to another to facilitate analysis of timing performance at different corners. Timing slack values produced by analysis are transformed to map them from one timing corner to another. The transformed timing slack values from multiple corners are amalgamated. The amalgamated timing slack values are used by a compilation phase (that potentially only understands a single corner) to optimize a logic design for multiple corners.

    摘要翻译： 优化逻辑设计，以满足多个过程/操作条件角的长途径和短路时序约束。 基于路径的编译阶段确定逻辑设计路径的实现，部分地通过监视从时序角度重要的一组路径并且评估一个或多个定时角上的一组被监控路径的定时性能。 基于时序分析的编译阶段确定将一组定时值从一个定时角转换到另一个时间角的转换。 编译阶段将时序延迟值从一个定时角转换到另一个定时角，以便于分析不同角落的时序性能。 通过分析产生的时间松弛值被转换，以将它们从一个时间点转到另一个时间点。 来自多个角落的转换后的时间松弛值是合并的。 合并的定时松弛值由编译阶段（可能只能理解单个角）使用，以优化多个角的逻辑设计。

    Clock switch-over circuits and methods
    3.
    发明授权
    Clock switch-over circuits and methods 有权
    时钟切换电路和方法

    公开(公告)号：US08248110B1

    公开(公告)日：2012-08-21

    申请号：US13048241

    申请日：2011-03-15

    申请人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

    发明人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz ,  Marcel A. LeBlanc

    IPC分类号： H01H71/22

    CPC分类号： G06F1/10

    摘要： Clock switch-over circuits and methods provide clock signals to clock routing networks. According to one embodiment, a multiplexer selects between a first clock signal and a second clock signal in response to a switch select signal received from a control circuit. A storage circuit stores an enable signal in response to an output clock signal of the multiplexer. A logic circuit transmits the output clock signal of the multiplexer to a clock routing network in response to the enable signal from the storage circuit. At least one signal is transmitted from the clock switch-over circuit to the control circuit.

    摘要翻译： 时钟切换电路和方法为时钟路由网络提供时钟信号。 根据一个实施例，多路复用器响应于从控制电路接收的开关选择信号在第一时钟信号和第二时钟信号之间进行选择。 存储电路响应于多路复用器的输出时钟信号而存储使能信号。 响应于来自存储电路的使能信号，逻辑电路将多路复用器的输出时钟信号传输到时钟路由网络。 至少一个信号从时钟切换电路发送到控制电路。

    Efficient delay elements
    4.
    发明授权
    Efficient delay elements 有权
    高效延时元件

    公开(公告)号：US07659764B2

    公开(公告)日：2010-02-09

    申请号：US12212314

    申请日：2008-09-17

    申请人： Ryan Fung ,  Vaughn Betz

    发明人： Ryan Fung ,  Vaughn Betz

    IPC分类号： H03K3/00

    CPC分类号： H03K19/17736 ,  H03K5/133 ,  H03K19/1778 ,  H03K19/17792 ,  H03K2005/00058 ,  H03K2005/00234

    摘要： Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths.

    摘要翻译： 提供了用于以功率和区域有效的方式延迟信号的电路，方法和装置。 可编程延迟元件的级内的门控元件抑制延迟元件的其他级的操作。 可编程延迟具有不同延迟的组件，其可以组合以在延迟增量的选择中提供灵活性，同时最小化延迟元件的面积。 延迟元件在不同的信号路径之间被共享，例如，以减少延迟元件的数量或允许利用其他信号路径的未使用的延迟元件。

    Periphery clock distribution network for a programmable logic device
    7.
    发明授权
    Periphery clock distribution network for a programmable logic device 有权
    用于可编程逻辑器件的周边时钟分配网络

    公开(公告)号：US07737751B1

    公开(公告)日：2010-06-15

    申请号：US11668521

    申请日：2007-01-30

    申请人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz

    发明人： Gary Lai ,  Andy L. Lee ,  Ryan Fung ,  Vaughn Betz

    IPC分类号： H03K3/013

    CPC分类号： G06F1/10

    摘要： A programmable logic device (PLD) includes a signal distribution network, separate from the high-quality, low-skew clock distribution networks of the PLD, for distributing, from peripheral input/output regions of the PLD, clock-type signals. The signal distribution network includes a central periphery clock bus, located near a group of peripheral input/output regions, for conducting clock-type signals from those regions onto a clock spine of the PLD. The clock spine may be dedicated to the signal distribution network, or may be part of a high-quality, low-skew clock distribution network covering all or part of the PLD. The signal distribution network allows greater skew than such high-quality, low-skew clock distribution networks, but nevertheless is of higher quality, and allows less skew, than the general programmable interconnect and routing resources.

    摘要翻译： 可编程逻辑器件（PLD）包括与PLD的高质量，低偏移时钟分配网络分离的信号分配网络，用于从PLD的外围输入/输出区域分配时钟型信号。 信号分配网络包括位于一组外围输入/输出区域附近的中央周边时钟总线，用于将这些区域的时钟信号传导到PLD的时钟脊上。 时钟脊可以专用于信号分配网络，或者可以是覆盖全部或部分PLD的高质量，低偏移时钟分配网络的一部分。 信号分配网络允许比这种高质量的低偏移时钟分配网络更大的偏斜，但是仍然具有比一般的可编程互连和路由资源更高的质量，并且允许较少的偏移。

    Efficient delay elements
    8.
    发明授权
    Efficient delay elements 有权
    高效延时元件

    公开(公告)号：US07629825B1

    公开(公告)日：2009-12-08

    申请号：US11549427

    申请日：2006-10-13

    申请人： Ryan Fung ,  Vaughn Betz

    发明人： Ryan Fung ,  Vaughn Betz

    IPC分类号： H03H11/26

    CPC分类号： H03K19/17736 ,  H03K5/133 ,  H03K19/1778 ,  H03K19/17792 ,  H03K2005/00058 ,  H03K2005/00234

    摘要： Circuits, methods, and apparatus for delaying signals in a power and area efficient manner are provided. A gating element within a stage of a programmable delay element suppresses an operation of other stages of the delay element. A programmable delay has components with differing delays that may be combined to give flexibility in choices for delay increments while minimizing the area of the delay element. A delay element is shared between different signal paths, for example, to reduce the number of delay elements or to allow utilizing unused delay elements of other signal paths.

    摘要翻译： 提供了用于以功率和区域有效的方式延迟信号的电路，方法和装置。 可编程延迟元件的级内的门控元件抑制延迟元件的其他级的操作。 可编程延迟具有不同延迟的组件，其可以组合以在延迟增量的选择中提供灵活性，同时最小化延迟元件的面积。 延迟元件在不同的信号路径之间被共享，例如，以减少延迟元件的数量或允许利用其他信号路径的未使用的延迟元件。

    Variable delay circuitry
    9.
    发明授权
    Variable delay circuitry 有权
    可变延迟电路

    公开(公告)号：US07138844B2

    公开(公告)日：2006-11-21

    申请号：US11083482

    申请日：2005-03-18

    申请人： Andy L. Lee ,  Gary Lai ,  Changsong Zhang ,  Vaughn Betz ,  Ryan Fung

    发明人： Andy L. Lee ,  Gary Lai ,  Changsong Zhang ,  Vaughn Betz ,  Ryan Fung

    IPC分类号： H03H11/26

    CPC分类号： H03K5/133 ,  H03K2005/00058

    摘要： Circuitry for providing an input data signal to other circuitry on an integrated circuit includes a course delay chain and a fine delay chain. These two delay chains are cascadable, if desired, to provide a very wide range of possible amounts of delay which can be finely graded by use of the fine delay chain.

    摘要翻译： 用于向集成电路上的其它电路提供输入数据信号的电路包括一个课程延迟链和一个精细延迟链。 如果需要，这两个延迟链是可级联的，以提供可以通过使用精细延迟链精细分级的可能的延迟量的非常宽的范围。