Underwater cleaning apparatus
    1.
    发明授权
    Underwater cleaning apparatus 失效
    水下清洗装置

    公开(公告)号:US4574722A

    公开(公告)日:1986-03-11

    申请号:US720457

    申请日:1985-04-05

    IPC分类号: B63B59/10

    CPC分类号: B63B59/10

    摘要: An underwater cleaning apparatus having a carrier, a plurality of wheels for shifting the position of the carrier along a submerged surface, a plurality of rotary brushes carried by the carrier and adapted to clean the submerged surface, and a source of power for rotating the rotary brushes. The apparatus further comprises flexible partition wall members for transmitting torque to the rotary brushes and forming reduced pressure chambers communicated with spaces formed by bristles of respective rotary brushes. As the rotary brushes rotate, the rotary brushes and the partition wall members in combination serve to provide vacuum to produce a force to press the carrier through the wheels onto the submerged surface to be cleaned. In addition, each of the rotary brushes are allowed to individually follow the configuration of the surface thanks to the flexibility of the partition wall members.

    摘要翻译: 一种具有载体的水下清洁装置,用于沿着浸没表面移动载体的位置的多个轮,由载体承载并适于清洁浸没表面的多个旋转刷,以及用于旋转旋转体的动力源 刷子 该装置还包括用于将扭矩传递到旋转刷的柔性分隔壁构件,并形成与相应旋转刷的刷毛形成的空间连通的减压室。 当旋转刷旋转时,组合的旋转刷和分隔壁构件用于提供真空以产生将载体通过轮按压到待清洁的浸没表面上的力。 此外,由于分隔壁构件的灵活性,每个旋转刷都允许单独地跟随表面的构造。

    Semiconductor integrated device and manufacturing method for the same
    2.
    发明申请
    Semiconductor integrated device and manufacturing method for the same 失效
    半导体集成器件及其制造方法相同

    公开(公告)号:US20110143523A1

    公开(公告)日:2011-06-16

    申请号:US12929870

    申请日:2011-02-22

    申请人: Hitoshi Okamoto

    发明人: Hitoshi Okamoto

    IPC分类号: H01L21/04

    摘要: A manufacturing method for a semiconductor integrated device including forming a second impurity layer of a second conductivity type that is higher in impurity concentration than a second well of the second conductivity type on a first impurity layer of a first conductivity type that is higher in impurity concentration than a first well of the first conductivity type, forming the first well of the first conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the first well being supplied with potential from the first impurity layer of the first conductivity type, and forming the second well of the second conductivity type on the second impurity layer of the second conductivity type on the first impurity layer of the first conductivity type, the second well being supplied with potential from the second impurity layer of the second conductivity type.

    摘要翻译: 一种半导体集成器件的制造方法,包括在杂质浓度高的第一导电型的第一杂质层上形成杂质浓度高于第二导电类型的第二导电类型的第二杂质层 比第一导电类型的第一阱,在第一导电类型的第一杂质层上在第二导电类型的第二杂质层上形成第一导电类型的第一阱,第一阱从第一导电类型的第一阱提供电位 在第一导电类型的第一杂质层上形成第二导电类型的第二杂质层上的第二导电类型的第二阱,第二阱由第二导电类型的第一杂质层提供电位, 第二导电类型的层。

    Circuitry and method of forming the same
    3.
    发明授权
    Circuitry and method of forming the same 失效
    电路及其形成方法

    公开(公告)号:US06320241B1

    公开(公告)日:2001-11-20

    申请号:US09375437

    申请日:1999-08-17

    申请人: Hitoshi Okamoto

    发明人: Hitoshi Okamoto

    IPC分类号: H01L2900

    摘要: A circuit between at least a connective terminal and at least a semiconductor circuit device includes at least a resistive element; a first interconnection inter-connecting a first side portion of the resistive element to the semiconductor circuit device; and a second interconnection inter-connecting a second side portion of the resistive element to the connective terminal, wherein at least a center portion except for the first and second side portions of the resistive element extends on a thin insulator portion which is provided on a semiconductor region, so that the thin insulator portion is sandwiched between the semiconductor region and the at least the center portion of the resistive element. The first and second portions of the resistive element extend on a thick insulator portion which is thicker than the thin insulator portion, and the semiconductor region is electrically connected to the second interconnection so as to allow a potential of the semiconductor region to follow a potential of the resistive element.

    摘要翻译: 至少连接端子和至少半导体电路器件之间的电路至少包括电阻元件; 电阻元件的第一侧部分与半导体电路器件相互连接的第一互连; 以及将所述电阻元件的第二侧部与所述连接端子相互连接的第二布线,其中除了所述电阻元件的所述第一侧面部分和所述第二侧面部分之外的至少一个中心部分在设置在半导体上的薄绝缘体部分上延伸 使得薄绝缘体部分夹在半导体区域和电阻元件的至少中心部分之间。 电阻元件的第一和第二部分在比绝缘体薄的部分厚的绝缘体部分上延伸,并且半导体区域与第二互连电连接,从而允许半导体区域的电位跟随 电阻元件。

    Signal processing apparatus, signal processing method, computer-readable medium and computer data signal
    4.
    发明授权
    Signal processing apparatus, signal processing method, computer-readable medium and computer data signal 有权
    信号处理装置,信号处理方法,计算机可读介质和计算机数据信号

    公开(公告)号:US08655107B2

    公开(公告)日:2014-02-18

    申请号:US12463310

    申请日:2009-05-08

    申请人: Hitoshi Okamoto

    发明人: Hitoshi Okamoto

    IPC分类号: G06K9/36

    CPC分类号: G06K9/00483 G06K9/00463

    摘要: An image processing apparatus includes an acquiring unit, a specifying unit, a search unit and a difference extracting unit. The acquiring unit acquires a first image and a second image. The specifying unit specifies one or more image areas included in the first image. The search unit searches the second image for an image area corresponding to each of the one or more image areas specified by the specifying unit. The difference extracting unit extracts a difference between the corresponding image area obtained by the search unit and each of the one or more image areas specified by the specifying unit.

    摘要翻译: 图像处理装置包括获取单元,指定单元,搜索单元和差异提取单元。 获取单元获取第一图像和第二图像。 指定单元指定包括在第一图像中的一个或多个图像区域。 搜索单元在第二图像中搜索与由指定单元指定的一个或多个图像区域中的每一个相对应的图像区域。 差异提取单元提取由搜索单元获得的相应图像区域与由指定单元指定的一个或多个图像区域中的每一个之间的差异。

    Semiconductor integrated circuit device
    5.
    发明申请
    Semiconductor integrated circuit device 有权
    半导体集成电路器件

    公开(公告)号:US20080185653A1

    公开(公告)日:2008-08-07

    申请号:US12010991

    申请日:2008-01-31

    IPC分类号: H01L27/088

    摘要: To reduce the leak current in the MOSFET connected between the pad and the ground. There are provided a pad PAD for an input or output signal, an n-type MOSFET M1a connected between the pad PAD and the ground and having its gate terminal and backgate connected in common, and a potential control circuit 10 that controls a potential Vb of the gate terminal and the backgate of the n-type MOSFET M1a based on a potential Vin of the pad PAD. The potential control circuit 10 comprises n-type MOSFETs M2 and M3; the n-type MOSFET M1a has its gate terminal and backgate connected to backgates and drains of the n-type MOSFETs M2 and M3; the n-type MOSFET M2 has its source grounded and its gate terminal connected to the pad PAD via a resistance R; and the n-type MOSFET M3 has its source connected to the pad PAD and its gate terminal grounded.

    摘要翻译: 以减少连接在焊盘和地之间的MOSFET中的漏电流。 提供用于输入或输出信号的焊盘PAD,连接在焊盘PAD和地之间并且其栅极端子和背板共同连接的n型MOSFET M 1 a和控制电位的电位控制电路10 基于焊盘PAD的电位Vin,栅极端子和n型MOSFET M1a的背栅极的Vb。 电位控制电路10包括n型MOSFET M 2和M 3; n型MOSFET M 1 a的栅极端子和背栅极连接到n型MOSFET M 2和M 3的后栅和漏极; n型MOSFET M 2的源极接地,其栅极端子通过电阻R连接到焊盘PAD; 并且n型MOSFET M 3的源极连接到焊盘PAD并且其栅极端子接地。

    Information management apparatus and method, image forming system apparatus and method, and computer readable medium and computer data signal therefor
    6.
    发明申请
    Information management apparatus and method, image forming system apparatus and method, and computer readable medium and computer data signal therefor 有权
    信息管理装置和方法,图像形成系统装置和方法以及计算机可读介质和计算机数据信号

    公开(公告)号:US20080130053A1

    公开(公告)日:2008-06-05

    申请号:US11822254

    申请日:2007-07-03

    申请人: Hitoshi Okamoto

    发明人: Hitoshi Okamoto

    IPC分类号: G06K15/00 G06K9/00

    摘要: An information management apparatus comprises: an assignment unit that uniquely assigns a region on an imaginary plane for a page of a document that is output by an image forming apparatus; a receiving unit that receives a request for assignment by the assignment unit, and identification information that identifies the document; a notification unit that notifies the image forming apparatus of coordinate values in a region assigned by the assignment unit, as coordinate values expressed on the document image of the page using a predetermined code; a storage unit that stores, for each region assigned by the assignment unit, region information that indicates the region and the identification information, the region information and the identification information being stored associated with each other; and a search unit that, when a coordinate value is input, searches for the identification information associated with the region that includes the coordinate value in the storage unit.

    摘要翻译: 信息管理装置包括:分配单元,其对由图像形成装置输出的文档的页面在虚拟平面上唯一地分配区域; 接收单元,其接收由所述分配单元分配的请求,以及标识所述文档的识别信息; 通知单元,其将所述分配单元分配的区域中的坐标值通知给所述图像形成装置,作为使用预定代码在所述页面的文档图像上表示的坐标值; 存储单元,对于由所述分配单元分配的每个区域,存储指示所述区域和所述识别信息的区域信息,所述区域信息和所述识别信息彼此相关联; 以及搜索单元,当输入坐标值时,搜索与包括存储单元中的坐标值的区域相关联的识别信息。

    Material processing apparatus, material processing method and material processing program
    7.
    发明申请
    Material processing apparatus, material processing method and material processing program 审中-公开
    材料加工设备,材料加工方法和材料加工程序

    公开(公告)号:US20060291723A1

    公开(公告)日:2006-12-28

    申请号:US11333258

    申请日:2006-01-18

    IPC分类号: G06K9/00 G09B7/00

    摘要: An material processing apparatus: includes: an original information storage unit that stores an electronic data on a material having an answer column; an image input unit that obtain an image data from the material in which the answer column is filled with an answer and an accuracy judgment on the answer is added; an original retrieval unit that retrieves an electronic data on an original of the material out of the stored data; a target area acquisition unit that grasps a recognition target area from the electronic data on the original; an additional data extraction unit that extracts additional contents in the recognition target area from the image data; a calculation unit that performs marking summation of the accuracy judgment; and a print unit that prints the marking summation result of accuracy on the material on which the accuracy judgment is added.

    摘要翻译: 一种材料处理装置:包括:原始信息存储单元,其存储关于具有答案列的材料的电子数据; 图像输入单元,从添加有回答列的材料获取图像数据,并且对答案进行精度判断; 原始检索单元,从所存储的数据中检索关于材料的原件的电子数据; 目标区域获取单元,从原件上的电子数据中掌握识别对象区域; 附加数据提取单元,从图像数据中提取识别目标区域中的附加内容; 执行精度判断的标记求和的计算单元; 以及打印单元,其在添加了精度判断的材料上打印精度的标记求和结果。

    Magnetoelectric generating system
    8.
    发明授权
    Magnetoelectric generating system 失效
    磁电发生系统

    公开(公告)号:US5206580A

    公开(公告)日:1993-04-27

    申请号:US854866

    申请日:1992-03-19

    CPC分类号: H02P9/305 H02P9/00

    摘要: The present invention is intended for maintaining constant the output voltage of a synchronous magnetoelectric generator without reducing the efficiency of the synchronous magnetoelectric generator regardless of load variation. A magnetoelectric generating system in accordance with the present invention comprises a synchronous magnetoelectric generator, a synchronous phase modifier connected to the output side of the synchronous magnetoelectric generator, a voltage detector for detecting the output voltage of the synchronous magnetoelectric generator, a comparator for comparing the output of the synchronous magnetoelectric generator detected by the voltage detector and a reference voltage set by means of a voltage setting device, an exciting current regulating circuit connected to the field winding of the synchronous phase modifier, and a controller. The controller controls the exciting current regulating circuit according to the output of the comparator.

    摘要翻译: 本发明旨在在不降低同步磁电发生器的效率的情况下保持同步磁电发生器的输出电压恒定,而不管负载变化如何。 根据本发明的磁电发电系统包括同步磁电发生器,连接到同步磁电发生器的输出侧的同步相位修正器,用于检测同步磁电发生器的输出电压的电压检测器,比较器 由电压检测器检测的同步磁电发生器的输出和通过电压设定装置设置的参考电压,连接到同步相位调节器的励磁绕组的励磁电流调节电路和控制器。 控制器根据比较器的输出控制励磁电流调节电路。

    Semiconductor device with a plurality of power supply systems
    9.
    发明授权
    Semiconductor device with a plurality of power supply systems 有权
    具有多个电源系统的半导体装置

    公开(公告)号:US08270132B2

    公开(公告)日:2012-09-18

    申请号:US12929206

    申请日:2011-01-07

    IPC分类号: H02H9/04

    摘要: A protection circuit that includes a first power supply system including a first power supply and a first ground, a second power supply system including a second power supply and a second ground, the second power supply system being connected to the first power supply system via a signal line through which signal transfer is performed between a circuit in the first power supply system and a circuit in the second power supply system, and a control circuit that, when coupled to an electro-static discharge (ESD) stress being applied to the first power supply system controls a switch, the switch being provided between the signal line and the first power supply.

    摘要翻译: 一种保护电路,其包括包括第一电源和第一接地的第一电源系统,包括第二电源和第二接地的第二电源系统,所述第二电源系统经由 在第一电源系统中的电路和第二电源系统中的电路之间执行信号传输的信号线,以及当耦合到施加到第一电源系统的静电放电(ESD)应力时的控制电路, 电源系统控制开关,开关设在信号线和第一电源之间。

    Semiconductor integrated circuit device including a pad and first mosfet
    10.
    发明授权
    Semiconductor integrated circuit device including a pad and first mosfet 有权
    半导体集成电路器件包括焊盘和第一mosfet

    公开(公告)号:US08008727B2

    公开(公告)日:2011-08-30

    申请号:US12010991

    申请日:2008-01-31

    IPC分类号: H01L23/62

    摘要: To reduce the leak current in the MOSFET connected between the pad and the ground. There are provided a pad PAD for an input or output signal, an n-type MOSFET M1a connected between the pad PAD and the ground and having its gate terminal and backgate connected in common, and a potential control circuit 10 that controls a potential Vb of the gate terminal and the backgate of the n-type MOSFET M1a based on a potential Vin of the pad PAD. The potential control circuit 10 comprises n-type MOSFETs M2 and M3; the n-type MOSFET M1a has its gate terminal and backgate connected to backgates and drains of the n-type MOSFETs M2 and M3; the n-type MOSFET M2 has its source grounded and its gate terminal connected to the pad PAD via a resistance R; and the n-type MOSFET M3 has its source connected to the pad PAD and its gate terminal grounded.

    摘要翻译: 以减少连接在焊盘和地之间的MOSFET中的漏电流。 提供用于输入或输出信号的焊盘PAD,连接在焊盘PAD和地之间并且其栅极端子和背板共同连接的n型MOSFET M1a和控制电位Vb的电位Vb的电位控制电路10 基于焊盘PAD的电位Vin的n型MOSFET M1a的栅极端子和背栅极。 电位控制电路10包括n型MOSFET M2和M3; n型MOSFET M1a的栅极端子和背栅极连接到n型MOSFET M2和M3的后栅和漏极; n型MOSFET M2的源极接地,其栅极端子通过电阻R连接到焊盘PAD; 并且n型MOSFET M3的源极连接到焊盘PAD并且其栅极端子接地。