DISPLAY CONTROLLER AND DISPLAY SYSTEM INCLUDING THE SAME
    1.
    发明申请
    DISPLAY CONTROLLER AND DISPLAY SYSTEM INCLUDING THE SAME 审中-公开
    显示控制器和显示系统,包括它们

    公开(公告)号:US20150213787A1

    公开(公告)日:2015-07-30

    申请号:US14547668

    申请日:2014-11-19

    Abstract: A display controller includes a scaler which is configured to receive a frame image, scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device, and output the frame image or the high resolution frame image to the display device for display. A method of controlling image display includes: receiving a frame image; determining whether to scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device; scaling up the frame image according to a result of the determining; and outputting the frame image or the high resolution frame image for display at the display device.

    Abstract translation: 显示控制器包括缩放器,其被配置为接收帧图像,基于帧图像的质量和关于显示设备的信息来缩放帧图像以生成高分辨率帧图像,并且输出帧图像或高 分辨率帧图像到显示设备进行显示。 控制图像显示的方法包括:接收帧图像; 基于所述帧图像的质量和关于显示装置的信息来确定是否放大所述帧图像以生成高分辨率帧图像; 根据确定的结果对帧图像进行放大; 并输出用于在显示装置显示的帧图像或高分辨率帧图像。

    SYSTEM-ON-CHIP HAVING SPECIAL FUNCTION REGISTER AND OPERATING METHOD THEREOF
    2.
    发明申请
    SYSTEM-ON-CHIP HAVING SPECIAL FUNCTION REGISTER AND OPERATING METHOD THEREOF 有权
    具有特殊功能寄存器的系统芯片及其操作方法

    公开(公告)号:US20140164726A1

    公开(公告)日:2014-06-12

    申请号:US14076300

    申请日:2013-11-11

    CPC classification number: G11C29/023 G11C11/5642

    Abstract: Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.

    Abstract translation: 示例性实施例公开了包括特殊功能寄存器(SFR)的片上系统(SoC)及其操作方法。 SFR包括第一更新存储元件,第二更新存储元件,对应于第一更新存储元件的第一更新逻辑,以及对应于第二更新存储元件的第二更新逻辑,其中时钟被提供给第一更新存储器 响应于所述第一更新逻辑被启用,并且响应于所述第二更新逻辑被使能而将所述时钟提供给所述第二更新存储元件。

    MEMORY SYSTEM AND SYSTEM ON CHIP INCLUDING THE SAME
    3.
    发明申请
    MEMORY SYSTEM AND SYSTEM ON CHIP INCLUDING THE SAME 审中-公开
    存储器系统和芯片系统,包括它们

    公开(公告)号:US20140173228A1

    公开(公告)日:2014-06-19

    申请号:US14072208

    申请日:2013-11-05

    CPC classification number: G06F5/12 G06F2205/126

    Abstract: In one example embodiment, a memory system includes a hierarchical first-in first-out (FIFO) memory configured to store data, and a FIFO controller configured to control inputting and outputting of data to and from the FIFO memory, wherein the FIFO memory includes a first layer. The first layer includes a high-speed input FIFO memory configured to receive data from an external device and a high-speed output FIFO memory configured to output data to the external device. The FIFO memory further includes a second layer. The second layer includes a main FIFO memory configured to receive data from the high-speed input FIFO memory and output data to the high-speed output FIFO memory.

    Abstract translation: 在一个示例性实施例中,存储器系统包括被配置为存储数据的分级先进先出(FIFO)存储器和配置成控制向FIFO存储器输入和输出数据的FIFO控制器,其中FIFO存储器包括 第一层 第一层包括被配置为从外部设备接收数据的高速输入FIFO存储器和被配置为向外部设备输出数据的高速输出FIFO存储器。 FIFO存储器还包括第二层。 第二层包括配置为从高速输入FIFO存储器接收数据并将数据输出到高速输出FIFO存储器的主FIFO存储器。

    RECONFIGURABLE IMAGE SCALING CIRCUIT
    4.
    发明申请
    RECONFIGURABLE IMAGE SCALING CIRCUIT 有权
    可重构图像调整电路

    公开(公告)号:US20150262337A1

    公开(公告)日:2015-09-17

    申请号:US14644383

    申请日:2015-03-11

    Abstract: A reconfigurable image scaling circuit includes a horizontal scalar, a bufferer, and a vertical scalar. The horizontal scalar is configured to generate a horizontally scaled image data by scaling an input image data horizontally. The bufferer includes a mapper and a plurality of buffers. The plurality of the buffers are configured to store the horizontally scaled image data. The vertical scalar is configured to generate an output image data by scaling the horizontally scaled image vertically using a vertical scaling method.

    Abstract translation: 可重构图像缩放电路包括水平标量,抛物面和垂直标量。 水平标量被配置为通过水平地缩放输入图像数据来生成水平缩放的图像数据。 缓冲器包括映射器和多个缓冲器。 多个缓冲器被配置为存储水平缩放的图像数据。 垂直标量被配置为通过使用垂直缩放方法垂直缩放水平缩放的图像来生成输出图像数据。

    FIRST-IN FIRST-OUT MEMORY DEVICE AND ELECTRONIC APPARATUS HAVING THE SAME
    5.
    发明申请
    FIRST-IN FIRST-OUT MEMORY DEVICE AND ELECTRONIC APPARATUS HAVING THE SAME 有权
    先进先出存储器件和具有该器件的电子设备

    公开(公告)号:US20130238822A1

    公开(公告)日:2013-09-12

    申请号:US13771295

    申请日:2013-02-20

    CPC classification number: G06F5/14 G06F5/065

    Abstract: A first-in first-out (FIFO) memory device includes a main FIFO unit, an auxiliary FIFO unit and a control unit. The main FIFO unit includes first through N-th one-port memories, each of which including M entries, where N and M are integers greater than or equal to two. The auxiliary FIFO unit includes one dual-port memory having M entries. The control unit performs a write operation by receiving a write command and data and storing the data in one of the main FIFO unit and the auxiliary FIFO unit based on an operating mode, and performs a read operation by receiving a read command and reading the data from one of the main FIFO unit and the auxiliary FIFO unit based on the operating mode

    Abstract translation: 先进先出(FIFO)存储器件包括主FIFO单元,辅助FIFO单元和控制单元。 主FIFO单元包括第一至第N个单端口存储器,每个存储器包括M个入口,其中N和M是大于或等于2的整数。 辅助FIFO单元包括一个具有M个条目的双端口存储器。 控制单元通过接收写入命令和数据并且基于操作模式将数据存储在主FIFO单元和辅助FIFO单元之一中来执行写入操作,并且通过接收读取命令并读取数据来执行读取操作 基于操作模式从主FIFO单元和辅助FIFO单元之一

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