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    MEMORY SYSTEM AND SYSTEM ON CHIP INCLUDING THE SAME
    2.
    发明申请
    MEMORY SYSTEM AND SYSTEM ON CHIP INCLUDING THE SAME 审中-公开
    存储器系统和芯片系统，包括它们

    公开(公告)号：US20140173228A1

    公开(公告)日：2014-06-19

    申请号：US14072208

    申请日：2013-11-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Han LEE ,  Jae-Sop KONG

    IPC: G06F12/02

    CPC classification number: G06F5/12 ,  G06F2205/126

    Abstract: In one example embodiment, a memory system includes a hierarchical first-in first-out (FIFO) memory configured to store data, and a FIFO controller configured to control inputting and outputting of data to and from the FIFO memory, wherein the FIFO memory includes a first layer. The first layer includes a high-speed input FIFO memory configured to receive data from an external device and a high-speed output FIFO memory configured to output data to the external device. The FIFO memory further includes a second layer. The second layer includes a main FIFO memory configured to receive data from the high-speed input FIFO memory and output data to the high-speed output FIFO memory.

    Abstract translation: 在一个示例性实施例中，存储器系统包括被配置为存储数据的分级先进先出（FIFO）存储器和配置成控制向FIFO存储器输入和输出数据的FIFO控制器，其中FIFO存储器包括 第一层 第一层包括被配置为从外部设备接收数据的高速输入FIFO存储器和被配置为向外部设备输出数据的高速输出FIFO存储器。 FIFO存储器还包括第二层。 第二层包括配置为从高速输入FIFO存储器接收数据并将数据输出到高速输出FIFO存储器的主FIFO存储器。

    FIRST-IN FIRST-OUT MEMORY DEVICE AND ELECTRONIC APPARATUS HAVING THE SAME
    5.
    发明申请
    FIRST-IN FIRST-OUT MEMORY DEVICE AND ELECTRONIC APPARATUS HAVING THE SAME 有权
    先进先出存储器件和具有该器件的电子设备

    公开(公告)号：US20130238822A1

    公开(公告)日：2013-09-12

    申请号：US13771295

    申请日：2013-02-20

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-Han LEE ,  Jae-Sop KONG

    IPC: G06F5/14

    CPC classification number: G06F5/14 ,  G06F5/065

    Abstract: A first-in first-out (FIFO) memory device includes a main FIFO unit, an auxiliary FIFO unit and a control unit. The main FIFO unit includes first through N-th one-port memories, each of which including M entries, where N and M are integers greater than or equal to two. The auxiliary FIFO unit includes one dual-port memory having M entries. The control unit performs a write operation by receiving a write command and data and storing the data in one of the main FIFO unit and the auxiliary FIFO unit based on an operating mode, and performs a read operation by receiving a read command and reading the data from one of the main FIFO unit and the auxiliary FIFO unit based on the operating mode

    Abstract translation: 先进先出（FIFO）存储器件包括主FIFO单元，辅助FIFO单元和控制单元。 主FIFO单元包括第一至第N个单端口存储器，每个存储器包括M个入口，其中N和M是大于或等于2的整数。 辅助FIFO单元包括一个具有M个条目的双端口存储器。 控制单元通过接收写入命令和数据并且基于操作模式将数据存储在主FIFO单元和辅助FIFO单元之一中来执行写入操作，并且通过接收读取命令并读取数据来执行读取操作 基于操作模式从主FIFO单元和辅助FIFO单元之一

    IMAGE COMBINATION DEVICE AND DISPLAY SYSTEM COMPRISING THE SAME
    6.
    发明申请
    IMAGE COMBINATION DEVICE AND DISPLAY SYSTEM COMPRISING THE SAME 审中-公开

    公开(公告)号：US20200051532A1

    公开(公告)日：2020-02-13

    申请号：US16655965

    申请日：2019-10-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dong-Han LEE ,  Min-Sao KIM ,  Jong-ho ROH ,  Sung-Hoo CHOI

    IPC: G09G5/377 ,  G06T1/20 ,  G09G5/36

    Abstract: Providing an image combination device and/or a display system comprising the same. The image combination device including an SGL control unit separating a plurality of layers into a first group layer and a second group layer not overlapping the first group layer, and a multi-layer blender combining the first group layer to produce a first composite image in a first frame and combining the second group layer including updated layers with the first composite image of the first frame to produce a second composite image in a second frame subsequent to the first frame.

    TRANSCEIVER AND OPERATION METHOD THEREOF
    7.
    发明申请
    TRANSCEIVER AND OPERATION METHOD THEREOF 有权
    收发器及其操作方法

    公开(公告)号：US20160080096A1

    公开(公告)日：2016-03-17

    申请号：US14848899

    申请日：2015-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hui-Jung KIM ,  Hyeong-Seok JEONG ,  Soo-Yong KIM ,  Jeong-Yeol BAE ,  Dong-Han LEE

    IPC: H04B17/318 ,  H04W52/02 ,  H04W4/00

    CPC classification number: H04B17/318 ,  H04W4/80 ,  H04W52/0209 ,  Y02B70/30 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/146 ,  Y02D70/162 ,  Y02D70/22

    Abstract: A transceiver and a method operating the transceiver are provided. The transceiver includes a first communication module configured to receive a first signal based on a first communication scheme; a second communication module configured to receive a second signal based on a second communication scheme; a reception module having a low-power circuit configured to detect a signal in a frequency band which can be used by the first communication module and the second communication module; and a controller configured to establish channels for the first communication module or the second communication module based on a strength of the signal detected by the reception module.

    Abstract translation: 提供了收发器和操作收发器的方法。 收发器包括：第一通信模块，被配置为基于第一通信方案接收第一信号; 第二通信模块，被配置为基于第二通信方案来接收第二信号; 具有低功率电路的接收模块，被配置为检测可由第一通信模块和第二通信模块使用的频带中的信号; 以及控制器，被配置为基于由所述接收模块检测到的信号的强度来建立用于所述第一通信模块或所述第二通信模块的信道。

    SYSTEM-ON-CHIP HAVING SPECIAL FUNCTION REGISTER AND OPERATING METHOD THEREOF
    8.
    发明申请
    SYSTEM-ON-CHIP HAVING SPECIAL FUNCTION REGISTER AND OPERATING METHOD THEREOF 有权
    具有特殊功能寄存器的系统芯片及其操作方法

    公开(公告)号：US20140164726A1

    公开(公告)日：2014-06-12

    申请号：US14076300

    申请日：2013-11-11

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Dong-Han LEE ,  Eun-Ji KANG ,  Jae-Sop KONG ,  Kee-Moon CHUN

    IPC: G11C29/02

    CPC classification number: G11C29/023 ,  G11C11/5642

    Abstract: Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.

    Abstract translation: 示例性实施例公开了包括特殊功能寄存器（SFR）的片上系统（SoC）及其操作方法。 SFR包括第一更新存储元件，第二更新存储元件，对应于第一更新存储元件的第一更新逻辑，以及对应于第二更新存储元件的第二更新逻辑，其中时钟被提供给第一更新存储器 响应于所述第一更新逻辑被启用，并且响应于所述第二更新逻辑被使能而将所述时钟提供给所述第二更新存储元件。

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