公开(公告)号：US20140164726A1

公开(公告)日：2014-06-12

申请号：US14076300

申请日：2013-11-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Han LEE ,  Eun-Ji KANG ,  Jae-Sop KONG ,  Kee-Moon CHUN

IPC: G11C29/02

CPC classification number: G11C29/023 ,  G11C11/5642

Abstract: Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.

Abstract translation: 示例性实施例公开了包括特殊功能寄存器（SFR）的片上系统（SoC）及其操作方法。 SFR包括第一更新存储元件，第二更新存储元件，对应于第一更新存储元件的第一更新逻辑，以及对应于第二更新存储元件的第二更新逻辑，其中时钟被提供给第一更新存储器 响应于所述第一更新逻辑被启用，并且响应于所述第二更新逻辑被使能而将所述时钟提供给所述第二更新存储元件。

公开(公告)号：US20170169256A1

公开(公告)日：2017-06-15

申请号：US15432601

申请日：2017-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyuck-Jun CHO ,  Donald NA ,  Seung-Hwan BAEK ,  Jae-Keun OH ,  Kee-Moon CHUN

IPC: G06K7/00 ,  G06K19/07

CPC classification number: G06K7/0021 ,  G06F1/00 ,  G06F1/06 ,  G06F1/3287 ,  G06K19/07 ,  G06K19/0701 ,  G06K19/0715 ,  G06Q20/341 ,  Y02D10/171 ,  Y02D50/20

Abstract: A smart card may include data storage and transmission circuitry, a plurality of voltage controllers to supply operational power to card circuitry, a plurality of oscillators to supply an internal clock for the card, and power management circuitry. The power management circuitry may be configured to shut down the oscillators and at least one, but not all, voltage controllers during a period after a data transmission is completed.

公开(公告)号：US20160225896A1

公开(公告)日：2016-08-04

申请号：US14993108

申请日：2016-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jae-Hyun YOO ,  Jin-Hyun NOH ,  Kee-Moon CHUN ,  Jong-Sung JEON

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10

CPC classification number: H01L29/7816 ,  H01L29/0619 ,  H01L29/063 ,  H01L29/165 ,  H01L29/7835 ,  H01L29/7848 ,  H01L29/7851

Abstract: A semiconductor device has reduced ON resistance (Ron) as well as a reduced electric field emanating from a current path. The semiconductor device includes a fin pattern, a gate electrode intersecting the fin pattern, a source region which has a first conductivity type and is disposed on one side of the gate electrode, a body region which has a second conductivity type, is situated within the fin pattern under the source region, and extends in a loop around the source region, a drain region which has the first conductivity type and is disposed on the other side of the gate electrode, a field dispersion region which has the second conductivity type and is situated within the fin pattern between the gate electrode and the drain region, and a drift region which has the first conductivity type, is situated within the fin pattern under the drain region and the field dispersion region, and extends in a loop around the drain region and the field dispersion region.

Abstract translation: 半导体器件具有降低的导通电阻（Ron）以及从电流路径发出的减小的电场。 半导体器件包括鳍状图案，与鳍状图案相交的栅极电极，具有第一导电类型并且设置在栅电极的一侧上的源极区域，具有第二导电类型的体区域位于 翅片图案，并且围绕源极区域以环形延伸，具有第一导电类型并设置在栅电极的另一侧的漏极区域，具有第二导电类型的场分散区域并且是 位于栅极电极和漏极区域之间的鳍状图案中，并且具有第一导电类型的漂移区域位于漏极区域和场分散区域下方的鳍状图案内，并且围绕漏极区域以环状延伸 和场分散区域。

公开(公告)号：US20160104701A1

公开(公告)日：2016-04-14

申请号：US14697707

申请日：2015-04-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Hyun YOO ,  Kee-Moon CHUN

IPC: H01L27/02 ,  H01L23/535 ,  H01L29/08 ,  H02H9/04 ,  H01L29/16 ,  H01L27/06 ,  H01L29/06 ,  H01L27/088 ,  H01L29/161

CPC classification number: H01L27/0274 ,  H01L23/535 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/7848 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including an electrostatic discharge (ESD) protection circuit includes an input port, a logic circuit receiving an input signal applied to the input port and generating an output signal based on the input signal, and an ESD protection circuit adjusting a level of the input signal when the level of the input signal exceeds a predetermined range. The ESD protection circuit includes a first fin and a second fin arranged on a semiconductor substrate in parallel, and a gate electrode formed in a direction crossing the first fin and the second fin, each of the first fin and the second fin includes a source region, a drain region, and a channel region disposed between the source region and the drain region, the channel region is disposed under the gate electrode, a source region of the first fin and a drain region of the second fin are disposed at a first side of the gate electrode, and a drain region of the first fin and a source region of the second fin are disposed at a second side of the gate electrode.

Abstract translation: 包括静电放电（ESD）保护电路的半导体器件包括输入端口，接收施加到输入端口的输入信号并基于输入信号产生输出信号的逻辑电路，以及ESD保护电路， 当输入信号的电平超过预定范围时输入信号。 ESD保护电路包括并联布置在半导体衬底上的第一鳍和第二鳍，以及沿与第一鳍和第二鳍交叉的方向形成的栅电极，每个第一鳍和第二鳍包括源极区域 漏极区域和设置在源极区域和漏极区域之间的沟道区域，沟道区域设置在栅电极下方，第一鳍片的源极区域和第二鳍片的漏极区域设置在第一侧面 并且第一鳍片的漏极区域和第二鳍片的源极区域设置在栅电极的第二侧。

公开(公告)号：US20150161416A1

公开(公告)日：2015-06-11

申请号：US14499724

申请日：2014-09-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ji-Myung NA ,  Kee-Moon CHUN

IPC: G06F21/72

CPC classification number: G06F21/60 ,  G06F21/71 ,  G06F21/84

Abstract: A security circuit may include a functional circuit including a test chain that connects flip-flops to verify hardware of the functional circuit, the functional circuit configured to generate an output signal by encrypting an input signal based on a control signal, a mode signal, and the chain; and/or a test controller configured to generate the input, control, and mode signals, and configured to generate an authentication result based on the output signal. A security circuit may include a first device including a plurality of flip-flops in a test chain, the first device configured to receive first, second, and third signals, and configured to generate a fourth signal by encrypting the first signal based on the second and third signals and the chain; and/or a second device configured to generate the first, second, and third signals, and configured to generate an authentication result based on the fourth signal.

Abstract translation: 安全电路可以包括功能电路，其包括连接触发器以验证功能电路的硬件的测试链，所述功能电路经配置以通过基于控制信号，模式信号和模式信号加密输入信号来产生输出信号 连锁，链条; 和/或测试控制器，被配置为生成输入，控制和模式信号，并且被配置为基于输出信号生成认证结果。 安全电路可以包括在测试链中包括多个触发器的第一设备，第一设备被配置为接收第一，第二和第三信号，并且被配置为通过基于第二信号加密第一信号来生成第四信号 和第三信号和链; 和/或第二设备，被配置为生成所述第一，第二和第三信号，并且被配置为基于所述第四信号生成认证结果。

公开(公告)号：US20140136861A1

公开(公告)日：2014-05-15

申请号：US14071801

申请日：2013-11-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soo-Yong KIM ,  Jun-Ho HUH ,  Kee-Moon CHUN

IPC: G06F1/26 ,  G06N5/04

CPC classification number: G06F1/3287 ,  G06F1/3206 ,  Y02D10/171

Abstract: A data request pattern generating device may include a sequence detector configured to generate data request sequence information based on a plurality of data request signals. The data request signals may be output from a plurality of function blocks. The device may include a time detector configured to generate data request time information based on the data request signals. The device may include a pattern generator configured to generate a data request pattern based on the data request sequence information and the data request time information.

Abstract translation: 数据请求模式生成装置可以包括：序列检测器，被配置为基于多个数据请求信号生成数据请求序列信息。 数据请求信号可以从多个功能块输出。 该设备可以包括被配置为基于数据请求信号产生数据请求时间信息的时间检测器。 该设备可以包括配置成基于数据请求序列信息和数据请求时间信息生成数据请求模式的模式发生器。