Abstract:
A display controller includes a scaler which is configured to receive a frame image, scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device, and output the frame image or the high resolution frame image to the display device for display. A method of controlling image display includes: receiving a frame image; determining whether to scale up the frame image to generate a high resolution frame image based on a quality of the frame image and information about a display device; scaling up the frame image according to a result of the determining; and outputting the frame image or the high resolution frame image for display at the display device.
Abstract:
Exemplary embodiments disclose a system-on-chip (SoC) including a special function register (SFR) and an operating method thereof. The SFR comprises a first update storage element, a second update storage element, a first update logic corresponding to the first update storage element, and a second update logic corresponding to the second update storage element, wherein a clock is supplied to the first update storage element in response to the first update logic being enabled, and the clock is supplied to the second update storage element in response to the second update logic being enabled.
Abstract:
In one example embodiment, a memory system includes a hierarchical first-in first-out (FIFO) memory configured to store data, and a FIFO controller configured to control inputting and outputting of data to and from the FIFO memory, wherein the FIFO memory includes a first layer. The first layer includes a high-speed input FIFO memory configured to receive data from an external device and a high-speed output FIFO memory configured to output data to the external device. The FIFO memory further includes a second layer. The second layer includes a main FIFO memory configured to receive data from the high-speed input FIFO memory and output data to the high-speed output FIFO memory.
Abstract:
A reconfigurable image scaling circuit includes a horizontal scalar, a bufferer, and a vertical scalar. The horizontal scalar is configured to generate a horizontally scaled image data by scaling an input image data horizontally. The bufferer includes a mapper and a plurality of buffers. The plurality of the buffers are configured to store the horizontally scaled image data. The vertical scalar is configured to generate an output image data by scaling the horizontally scaled image vertically using a vertical scaling method.
Abstract:
A first-in first-out (FIFO) memory device includes a main FIFO unit, an auxiliary FIFO unit and a control unit. The main FIFO unit includes first through N-th one-port memories, each of which including M entries, where N and M are integers greater than or equal to two. The auxiliary FIFO unit includes one dual-port memory having M entries. The control unit performs a write operation by receiving a write command and data and storing the data in one of the main FIFO unit and the auxiliary FIFO unit based on an operating mode, and performs a read operation by receiving a read command and reading the data from one of the main FIFO unit and the auxiliary FIFO unit based on the operating mode