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公开(公告)号：US20250022900A1
公开(公告)日：2025-01-16
申请号：US18618477
申请日：2024-03-27
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jinyoung KIM , Junghyun Kim , Junsik Lee , Jonghoon Park , Yun Ki Lee
IPC: H01L27/146
Abstract: An image sensor includes: a substrate including a first side and a second side facing the first side; pixels including a photoelectric conversion layer in the substrate and a transistor on the first side of the substrate; and a pixel separating pattern between the pixels, wherein the pixel separating pattern includes a first separating pattern, a second separating pattern, and a third separating pattern, the second separating pattern is conductive, and the first separating pattern and the third separating pattern are non-conductive, the second separating pattern is nearer the first side of the substrate than is the third separating pattern, and a first end of the first separating pattern, a first end of the second separating pattern, and a first end of the third separating pattern are on the second side of the substrate.
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公开(公告)号：US20240221843A1
公开(公告)日：2024-07-04
申请号：US18470931
申请日：2023-09-20
Applicant: Samsung Electronics Co., Ltd.
Inventor： Minji CHO , Jisang LEE , Sehwan PARK , Jinyoung KIM , Joonsuc JANG
CPC classification number: G11C16/26 , G11C16/0433 , G11C16/08
Abstract: Disclosed is a method of operating a memory device including a memory cell array. The memory cell array includes a plurality of memory cells and a plurality of word lines connected to the plurality of memory cells. The method includes performing an additional read operation on the plurality of memory cells by adjusting a voltage level applied to a selected word line WLN connected to memory cells to be additionally read for improvements in memory cell sensing characteristics and a voltage level applied to a plurality of unselected word lines WLUnselect, and performing a main read operation on the plurality of memory cells by adjusting a voltage level applied to at least one first word line among the plurality of unselected word lines WLUnselect to be different from a voltage level applied to the at least one first word line in the additional read operation.
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3.发明公开公开(公告)号：US20240029814A1
公开(公告)日：2024-01-25
申请号：US18374026
申请日：2023-09-28
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehwan PARK , Jinyoung KIM , Ilhan PARK , Kyoman KANG , Sangwan NAM
CPC classification number: G11C29/50004 , G11C7/1039 , G11C7/1045 , G11C7/1057 , G11C7/1084 , G11C8/18 , G11C16/28 , G11C29/44 , G11C2029/1202
Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.
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公开(公告)号：US20220276802A1
公开(公告)日：2022-09-01
申请号：US17522578
申请日：2021-11-09
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Youngdeok SEO , Jinyoung KIM , Sehwan PARK , Ilhan PARK
IPC: G06F3/06
Abstract: A nonvolatile memory device includes a memory block including a memory area, an on-chip valley search (OVS) circuit performing an OVS sensing operation on the memory block, and a buffer memory storing at least one variation table including variation information of a threshold voltage of memory cells, obtained from the OVS sensing operation. A reading operation including an OVS sensing operation and a main sensing operation on the memory area is performed in response to a read command applied by a memory controller, the OVS sensing operation is performed at an OVS sensing level, and the main sensing operation is performed at a main sensing level reflecting the variation information. In the nonvolatile memory device, correction accuracy for deterioration of a word line threshold voltage may be improved, and a burden on a memory controller may be reduced.
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公开(公告)号：US20220199164A1
公开(公告)日：2022-06-23
申请号：US17503197
申请日：2021-10-15
Applicant: Samsung Electronics Co., Ltd.
Inventor： Jinyoung KIM , Sehwan PARK , Ilhan PARK , Youngdeok SEO , Dongmin SHIN
Abstract: A memory device may include a memory block and a control circuit. The memory block may include a first sub-block and a second sub-block that are connected between a common source line and a plurality of bit lines and may be vertically stacked. The control circuit may be configured to select any one of the common source line and the plurality of bit lines as a transmission path of an erase voltage based on positions of the first sub-block and the second sub-block, and perform erase operations on the first sub-block and the second sub-block in units of sub-blocks.
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Patent Agency Ranking
公开(公告)号：US20240379923A1
公开(公告)日：2024-11-14
申请号：US18627177
申请日：2024-04-04
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Jonghoon JUNG , Jinyoung KIM , Sungyong MIN , Changjoon LEE
IPC: H01L33/62 , H01L25/075 , H01L33/46
Abstract: A display module includes: a substrate including a mounting surface and a pad electrode on the mounting surface; an inorganic light emitting element including a contact electrode corresponding to the pad electrode; a bump disposed between the pad electrode and the contact electrode to bond the pad electrode and the contact electrode, the bump being electrically connecting the pad electrode to the contact electrode; a reflective member configured to underfill the inorganic light emitting element to cover side surfaces of the inorganic light emitting element and a bottom surface of the inorganic light emitting element, and configured to reflect light; and a cover member configured to cover side surfaces of the reflective member and the mounting surface of the substrate, the cover member having a black color.
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公开(公告)号：US20230217169A1
公开(公告)日：2023-07-06
申请号：US18183477
申请日：2023-03-14
Applicant: Samsung Electronics Co., Ltd.
Inventor： Min LEE , Jinyoung KIM , Hanki YOON , Soonkyu LEE , Jongkwang JUNG
CPC classification number: H04R3/12 , H04R5/02 , H04S3/008 , H04R5/04 , H04S2400/01 , H04R2499/15 , H04R2499/11
Abstract: An electronic device is provided. The electronic device includes a plurality of audio output devices and at least one processor operatively connected to the plurality of audio output devices, wherein the at least one processor may be configured to identify orientation information of the electronic device, based on detecting an output of audio data, transmit, to each audio output device, channel information of audio data to be output by each of the plurality of audio output devices, based on the orientation information of the electronic device, and control the plurality of audio output devices so that each audio output device selects a channel and outputs audio data of the selected channel, based on the channel information.
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8.发明公开公开(公告)号：US20230188917A1
公开(公告)日：2023-06-15
申请号：US18101889
申请日：2023-01-26
Applicant: Samsung Electronics Co., Ltd.
Inventor： Soonkyu LEE , Taemin KWON , Jinyoung KIM , Dongmoon OK , Jongmin CHOI
CPC classification number: H04S5/02 , G06F3/162 , H04S1/007 , H04S3/008 , H04S2400/01
Abstract: An electronic device includes: an Application Processor (AP) including a CPU; and an audio processing unit configured to: receive an audio stream of M channels from the CPU, convert the M-channel audio stream into an N-channel audio stream, the N-channel being different from the M-channel, output the N-channel audio stream through an output device. The audio processing unit is further configured to: detect a connection with the external electronic device through an audio output interface; determine whether to stop the converting the M-channel audio stream into the N-channel audio stream, based on information received from the CPU; and transmit, via the audio output interface, the M-channel audio stream to the external electronic device in response to the determination of stopping the converting the M-channel audio stream into the N-channel audio stream.
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公开(公告)号：US20220277801A1
公开(公告)日：2022-09-01
申请号：US17749607
申请日：2022-05-20
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehwan PARK , Jinyoung KIM , Ilhan PARK , Kyoman KANG , Sangwan NAM
Abstract: A non-volatile memory device includes a memory cell array including a plurality of memory blocks that includes a plurality of memory cells connected to a plurality of word lines and a plurality of bit lines, a row decoder configured to select one among the plurality of memory blocks, based on an address, a voltage generator configured to apply word line voltages corresponding to selected word lines and unselected word lines, among the plurality of word lines, page buffers connected to the plurality of bit lines and configured to read data from a memory cell connected to one among the selected word lines of the selected one among the plurality of memory blocks, and a control logic configured to control the row decoder, the voltage generator, and the page buffers.
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公开(公告)号：US20220254433A1
公开(公告)日：2022-08-11
申请号：US17469422
申请日：2021-09-08
Applicant: SAMSUNG ELECTRONICS CO., LTD.
Inventor： Sehwan PARK , Jinyoung KIM , Youngdeok SEO , Dongmin SHIN , Joonsuc JANG , Sungmin JOE
Abstract: A storage device includes a nonvolatile memory device and a memory controller to control the nonvolatile memory device. The nonvolatile memory device includes a memory cell array. The memory cell array includes a normal cell region, a parity cell region and a redundancy cell region. First bit-lines are connected to the normal cell region and the parity cell region and second bit-lines are connected to the redundancy cell region. The memory controller includes an error correction code (ECC) engine to generate parity data. The memory controller stores user data in the normal cell region, controls the nonvolatile memory device to perform a column repair on first defective bit-lines among the first bit-lines, assigns additional column addresses to the first defective bit-lines and the second bit-lines and stores at least a portion of the parity data in a region corresponding to the additionally assigned column addresses.
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