公开(公告)号：US20250105223A1

公开(公告)日：2025-03-27

申请号：US18773012

申请日：2024-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook HAN ,  Kyoungmin LEE ,  Kyungsoo LEE ,  Junho HUH

IPC: H01L25/10 ,  H01L25/065 ,  H03F3/24 ,  H05K1/18

Abstract: A radio frequency communication device may include a first package including a first semiconductor chip, the first semiconductor chip including a reception amplifier configured to receive a radio frequency (RF) signal, amplify the received RF signal, and output the amplified RF signal, a second package including a second semiconductor chip and a third semiconductor chip, the second semiconductor chip including a reception chain configured to receive the amplified RF signal from the first semiconductor chip via at least one first wire on a printed circuit board (PCB), and generate a baseband digital signal, and the third semiconductor chip being configured to receive the baseband digital signal from the second semiconductor chip via an internal transmission of the second package, and process the baseband digital signal, and the PCB on which the first package and the second package are mounted.

公开(公告)号：US20250132775A1

公开(公告)日：2025-04-24

申请号：US18768569

申请日：2024-07-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook HAN ,  Kyoungmin LEE ,  Kyungsoo LEE ,  Junho HUH

IPC: H04B1/00 ,  H03F3/19

Abstract: A radio frequency integrated circuit (RFIC) includes a first receive chain configured to receive a first high-frequency input signal, generate a first baseband signal based on the first high-frequency input signal by using a first downward frequency signal, and output the first baseband signal to a first output port, a first local oscillator configured to generate a first oscillation clock signal, a second local oscillator configured to generate a second oscillation clock signal, a first multiplexer configured to output one among the first and oscillation clock signals to a second output port based on an oscillation clock output selection signal, a first input port configured to receive a third oscillation clock signal from an external source, and a second multiplexer configured to output one among the first through third oscillation signals to the first receive chain as the first downward frequency signal based on a first downward frequency selection signal.

公开(公告)号：US20230206830A1

公开(公告)日：2023-06-29

申请号：US17986367

申请日：2022-11-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changju LEE ,  Kyoungmin LEE

IPC: G09G3/3225 ,  H01L25/16 ,  H01L23/00 ,  G09G3/20 ,  G06F3/041 ,  G06V40/13

CPC classification number: G09G3/3225 ,  H01L25/167 ,  H01L24/08 ,  G09G3/2096 ,  G06F3/0416 ,  G06V40/13 ,  H01L27/3244

Abstract: A stacked display driver integrated circuit (DDIC) configured to drive a display panel of a display device includes a first circuit and a second circuit. The first circuit is formed by a low-end process according to a first design rule such that the first circuit has a first critical dimension. The second circuit is formed by a high-end process according to a second design rule smaller than the first design rule such that the second circuit has a second critical dimension smaller than the first critical dimension. The first circuit and the second circuit are stacked in a vertical direction. The size of the stacked DDIC may be reduced by stacking, in the vertical direction, the first circuit including analog circuits and the second circuit including digital circuits.