公开(公告)号：US20250105223A1

公开(公告)日：2025-03-27

申请号：US18773012

申请日：2024-07-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook HAN ,  Kyoungmin LEE ,  Kyungsoo LEE ,  Junho HUH

IPC: H01L25/10 ,  H01L25/065 ,  H03F3/24 ,  H05K1/18

Abstract: A radio frequency communication device may include a first package including a first semiconductor chip, the first semiconductor chip including a reception amplifier configured to receive a radio frequency (RF) signal, amplify the received RF signal, and output the amplified RF signal, a second package including a second semiconductor chip and a third semiconductor chip, the second semiconductor chip including a reception chain configured to receive the amplified RF signal from the first semiconductor chip via at least one first wire on a printed circuit board (PCB), and generate a baseband digital signal, and the third semiconductor chip being configured to receive the baseband digital signal from the second semiconductor chip via an internal transmission of the second package, and process the baseband digital signal, and the PCB on which the first package and the second package are mounted.

公开(公告)号：US20240096714A1

公开(公告)日：2024-03-21

申请号：US18462067

申请日：2023-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo LEE ,  Junho HUH

IPC: H01L21/66 ,  H01L21/56 ,  H01L23/528 ,  H10B20/25

CPC classification number: H01L22/22 ,  H01L21/56 ,  H01L23/528 ,  H10B20/25

Abstract: Provided are a semiconductor chip and a method of manufacturing a semiconductor package including the semiconductor chip. The semiconductor chip includes a front end of line (FEOL) including an active layer, a back end of line (BEOL) including a plurality of metal layers including a wire, an optional dicing line along which dicing is optionally performed, and an isolation block configured to process a signal for a discontinuous wire when the wire is discontinuous by being diced along the optional dicing line, and a chip die on which the active layer is not formed around a cross section cut by the optional dicing line. Thus, the production yield of the semiconductor chip may be improved, and the production costs thereof may be reduced.

公开(公告)号：US20200348707A1

公开(公告)日：2020-11-05

申请号：US16935684

申请日：2020-07-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungsoo LEE ,  Junghun HEO

IPC: G05F1/575

Abstract: A power management device includes at least one switching regulator to generate a conversion voltage from an input voltage, a plurality of low drop-out regulators to generate a plurality of output voltages from the conversion voltage, and a controller to estimate drop-out voltages of the low drop-out regulators based on output currents of the low drop-out regulators and to dynamically control the conversion voltage based on the estimated drop-out voltages.

公开(公告)号：US20210271276A1

公开(公告)日：2021-09-02

申请号：US17027946

申请日：2020-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minshik SEOK ,  Younghoon LEE ,  Kyungrae KIM ,  Kyungsoo LEE ,  Junho HUH

IPC: G05F1/56

Abstract: Multiple power management integrated circuits (PMICs) may perform communication and power sequence operation coordination between the multiple PMICs through a communication interface connected to two signal lines using a dual pin interface. The multiple PMICs include a main PMIC configured to communicate with at least one application processor through a system interface and at least one sub-PMIC configured to communicate with the main PMIC through the communication interface. A first signal line uses a single bidirectional signaling scheme, and a power status signal PSTATUS is exchanged between the main PMIC and the at least one sub-PMIC through the first signal line. A second signal line uses a single unidirectional signaling scheme, and a power sequence control signal PIF is transmitted from the main PMIC to the at least one sub-PMIC through the second signal line.

公开(公告)号：US20180032095A1

公开(公告)日：2018-02-01

申请号：US15480528

申请日：2017-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungsoo LEE ,  Junghun HEO

IPC: G05F1/575

CPC classification number: G05F1/575

Abstract: A power management device includes at least one switching regulator to generate a conversion voltage from an input voltage, a plurality of low drop-out regulators to generate a plurality of output voltages from the conversion voltage, and a controller to estimate drop-out voltages of the low drop-out regulators based on output currents of the low drop-out regulators and to dynamically control the conversion voltage based on the estimated drop-out voltages.

公开(公告)号：US20240427405A1

公开(公告)日：2024-12-26

申请号：US18749071

申请日：2024-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo LEE ,  Sooyong KIM ,  Younghoon LEE ,  Jongjin LEE ,  Junho HUH

IPC: G06F1/324

Abstract: A Dynamic Voltage and Frequency Scaling (DVFS) controller, an integrated circuit including DVFS, and a method of operating the DVFS controller are provided. The integrated circuit includes at least one subblock circuit configured to process an instruction, and a DVFS controller configured to control a power management unit (PMU) and a clock management unit (CMU) to control an operating voltage and an operating frequency, respectively, based on a resonance frequency calculated from a frequency response resulting from dynamic characteristics of an entire power system including the PMU, a power delivery network (PDN), and the subblock circuit.

公开(公告)号：US20230162779A1

公开(公告)日：2023-05-25

申请号：US17881208

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungsoo LEE ,  Yoonjick LEE

IPC: G11C11/4074 ,  G11C11/4093 ,  G11C7/24 ,  H03L7/099

CPC classification number: G11C11/4074 ,  G11C7/24 ,  G11C11/4093 ,  H03L7/0995

Abstract: Provided are an electronic device and an operating method thereof. The electronic device includes a nonvolatile memory; a power management integrated circuit configured to generate operating power based on supply power received from a power source, and generate first time information independent of the supply power; and an application processor configured to receive the operating power, generate second time information, obtain, based on the generation of the operating power being interrupted, the first time information, and output, to the nonvolatile memory, time data including the first time information and the second time information, a write command, and an address.

公开(公告)号：US20230155574A1

公开(公告)日：2023-05-18

申请号：US17889543

申请日：2022-08-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyungsoo LEE

IPC: H03K3/011 ,  H03K17/687 ,  H03K3/012

CPC classification number: H03K3/011 ,  H03K17/6872 ,  H03K3/012 ,  H03K17/6874

Abstract: An output driver is provided. The output driver includes: a pull-up driver connected between an output power supply voltage and an output node, and configured to pull up a voltage at the output node based on a pull-up driving signal and a pull-up reference voltage; a pull-down driver connected between the output node and a ground voltage, and configured to pull down the voltage at the output node based on a pull-down driving signal and a pull-down reference voltage; and a reference voltage compensation circuit configured to perform a short operation during transitions of the pull-up driving signal and the pull-down driving signal, wherein the short operation includes electrically connecting any one or any combination of the pull-up reference voltage to the ground voltage, and the pull-down reference voltage to the output power supply voltage.

公开(公告)号：US20220155807A1

公开(公告)日：2022-05-19

申请号：US17665907

申请日：2022-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minshik SEOK ,  Younghoon LEE ,  Kyungrae KIM ,  Kyungsoo LEE ,  Junho HUH

IPC: G05F1/56 ,  G06F1/26

Abstract: Multiple power management integrated circuits (PMICs) may perform communication and power sequence operation coordination between the multiple PMICs through a communication interface connected to two signal lines using a dual pin interface. The multiple PMICs include a main PMIC configured to communicate with at least one application processor through a system interface and at least one sub-PMIC configured to communicate with the main PMIC through the communication interface. A first signal line uses a single bidirectional signaling scheme, and a power status signal PSTATUS is exchanged between the main PMIC and the at least one sub-PMIC through the first signal line. A second signal line uses a single unidirectional signaling scheme, and a power sequence control signal PIF is transmitted from the main PMIC to the at least one sub-PMIC through the second signal line.