公开(公告)号：US20170194210A1

公开(公告)日：2017-07-06

申请号：US15292157

申请日：2016-10-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Tae-hwan OH ,  Kwang-sub YOON ,  Yong-chul JEONG ,  Seung-ho OH ,  Ji-young CHOI ,  Suk-won LEE ,  Woo-jeong SHIN ,  Myoung-ki JUNG ,  Min-jung KIM

IPC: H01L21/8234 ,  H01L21/311 ,  H01L21/02 ,  H01L21/28 ,  H01L27/088

CPC classification number: H01L21/823456 ,  H01L21/02112 ,  H01L21/02115 ,  H01L21/02118 ,  H01L21/02282 ,  H01L21/28123 ,  H01L21/31138 ,  H01L21/823431 ,  H01L29/42376

Abstract: A semiconductor device including a substrate including a first and second region; a first active region formed in an upper portion of the substrate in the first region; a second active region formed in an upper portion of the substrate in the second region; a first gate structure extending across the first active region, having a first gate length, and including a first high-k dielectric layer, a first lower metal layer, and a first upper metal layer; a second gate structure extending across the second active region, having a second gate length, and including a second high-k dielectric layer, a second lower metal layer having at least one metal layer, and a second upper metal layer; and spacers at sides of each of the first and second gate structures, a cross section of each of the first and second high-k dielectric layers has a U-shape, a cross section of each of the first and second lower metal layers has a U-shape, the first and second lower metal layers covering bottom surfaces and inner side surfaces of the corresponding first and second high-k dielectric layers, respectively, the first high-k dielectric and first lower metal layer are buried under the first upper metal layer, and the second high-k dielectric and second lower metal layer are buried under the second upper metal layer.