公开(公告)号：US12057404B2

公开(公告)日：2024-08-06

申请号：US17644716

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanmin Jo ,  Taeyoon Kim ,  Seungki Nam ,  Sungwook Moon

IPC: H01L23/48 ,  H01L21/48 ,  H01L23/538 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  H01L23/367 ,  H01L23/498

CPC classification number: H01L23/5386 ,  H01L21/486 ,  H01L25/0652 ,  H01L25/18 ,  H01L23/3675 ,  H01L23/49811 ,  H01L23/5384 ,  H01L24/16 ,  H01L2224/16227

Abstract: A semiconductor device includes pads of a first group and a plurality of first peripheral pads, which are adjacent to each other and spaced apart by a first horizontal gap in a first direction, and pads of a first group and a plurality of first peripheral pads, which are connected to each other and spaced apart by a first vertical gap, greater than the first horizontal gap, in a second direction. A plurality of first wiring patterns include first horizontal extension portions extending at an angle exceeding about 45 degrees with respect to the first direction within the first horizontal gap.

公开(公告)号：US12107034B2

公开(公告)日：2024-10-01

申请号：US17517291

申请日：2021-11-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Shaofeng Ding ,  Sungwook Moon ,  Jeonghoon Ahn ,  Yunki Choi

IPC: H01L21/00 ,  H01L23/48 ,  H01L23/522 ,  H01L25/065

CPC classification number: H01L23/481 ,  H01L23/5226 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A semiconductor chip may include; a device layer including transistors on a substrate, a wiring layer on the device layer, a first through via passing through the device layer and the substrate, and a second through via passing through the wiring layer, the device layer and the substrate, wherein a first height of the first through via is less than a second height of the second through via.

公开(公告)号：US20220344272A1

公开(公告)日：2022-10-27

申请号：US17644716

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanmin Jo ,  Taeyoon Kim ,  Seungki Nam ,  Sungwook Moon

IPC: H01L23/538 ,  H01L25/18 ,  H01L25/065 ,  H01L21/48

Abstract: A semiconductor device includes pads of a first group and a plurality of first peripheral pads, which are adjacent to each other and spaced apart by a first horizontal gap in a first direction, and pads of a first group and a plurality of first peripheral pads, which are connected to each other and spaced apart by a first vertical gap, greater than the first horizontal gap, in a second direction. A plurality of first wiring patterns include first horizontal extension portions extending at an angle exceeding about 45 degrees with respect to the first direction within the first horizontal gap.

公开(公告)号：US11144699B2

公开(公告)日：2021-10-12

申请号：US17018262

申请日：2020-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungki Nam ,  Jungil Son ,  Sungwook Moon

IPC: G06F30/00 ,  G06F30/392 ,  G06F30/39

Abstract: Disclosed is a method implemented with a computer system executing instructions for a semiconductor design simulation. The method includes generating a plurality of floor plans placing a plurality of circuit blocks differently, generating a plurality of power models from the plurality of floor plans, and selecting a layout corresponding to one of the plurality of floor plans by selecting at least one power model satisfying system requirements from among the plurality of power models.

公开(公告)号：US11068636B2

公开(公告)日：2021-07-20

申请号：US16835423

申请日：2020-03-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoonjae Hwang ,  Sungwook Moon

IPC: G06F30/392 ,  H01L23/498 ,  H01L23/522 ,  G06F30/373 ,  H01L25/065 ,  H01L25/00 ,  H01L21/48

Abstract: A design method for a semiconductor package including a first chip, a second chip, a 2.5 dimensional (2.5D) interposer, a package substrate, and a board includes generating a layout including the 2.5D interposer on the package substrate and the first and second chips individually arranged on the 2.5D interposer, based on design information; analyzing signal integrity and power integrity between the first and second chips from the layout; analyzing signal integrity or power integrity between the first chip and at least one third chip on the board from the layout; and determining whether to modify the layout based on the analysis results.