公开(公告)号：US11631695B2

公开(公告)日：2023-04-18

申请号：US17085735

申请日：2020-10-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar

IPC: H01L23/522 ,  H01L27/11582 ,  H01L27/11556 ,  G11C8/14 ,  H01L27/1157 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill structures located within the memory openings can include a respective memory film and a respective vertical semiconductor channel.

公开(公告)号：US11594553B2

公开(公告)日：2023-02-28

申请号：US17150561

申请日：2021-01-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar

IPC: H01L27/11597 ,  H01L27/1159 ,  H01L27/11587 ,  H01L27/11563 ,  H01L27/11578 ,  H01L27/11582

Abstract: A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. Each memory element within the vertical stack of memory elements includes a crystalline ferroelectric memory material portion and an epitaxial template portion.

公开(公告)号：US11521984B2

公开(公告)日：2022-12-06

申请号：US16910752

申请日：2020-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11524 ,  H01L27/11519 ,  H01L27/11565

Abstract: A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall of each vertical semiconductor channel in the memory opening fill structures. A metal-containing layer is deposited on physically exposed surfaces of the vertical semiconductor channel and the vertical semiconductor channel is crystallized using metal-induced lateral crystallization. Alternatively or additionally, cylindrical metal-semiconductor alloy regions can be formed around the vertical semiconductor channels to reduce contact resistance. A source contact layer can be formed in the source cavity.

公开(公告)号：US11239253B2

公开(公告)日：2022-02-01

申请号：US16917597

申请日：2020-06-30

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou

IPC: H01L21/00 ,  H01L27/11582 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11543 ,  H01L27/11573

Abstract: A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.

公开(公告)号：US11121140B2

公开(公告)日：2021-09-14

申请号：US16737088

申请日：2020-01-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seung-Yeul Yang ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar ,  Rahul Sharangpani

IPC: H01L47/00 ,  H01L27/11514 ,  H01L49/02 ,  H01L27/11504 ,  H01L45/00 ,  H01L23/528

Abstract: A ferroelectric tunnel junction memory device includes a bit line, a word line and a memory cell located between the bit line and the word line. The memory cell includes a ferroelectric tunneling dielectric portion and an ovonic threshold switch material portion.

公开(公告)号：US11049880B2

公开(公告)日：2021-06-29

申请号：US16530256

申请日：2019-08-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Fei Zhou ,  Rahul Sharangpani ,  Raghuveer S. Makala

IPC: H01L27/11597 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11587 ,  H01L27/11565 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1159

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical stack of single crystalline ferroelectric dielectric layers and a respective vertical semiconductor channel.

公开(公告)号：US10381559B1

公开(公告)日：2019-08-13

申请号：US16002169

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Christopher J. Petti ,  Rahul Sharangpani ,  Adarsh Rajashekhar ,  Seung-Yeul Yang

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Alternating stacks of insulating strips and sacrificial material strips are formed over a substrate. A laterally alternating sequence of pillar cavities and pillar structures can be formed within each of the line trenches. A phase change memory cell including a discrete metal portion, a phase change memory material portion, and a selector material portion is formed at each level of the sacrificial material strips at a periphery of each of the pillar cavities. Vertical bit lines are formed in the two-dimensional array of pillar cavities. Remaining portions of the sacrificial material strips are replaced with electrically conductive word line strips. Pathways for providing an isotropic etchant for the sacrificial material strips and a reactant for a conductive material of the electrically conductive word line strips may be provided by a backside trench, or by removing the pillar structures to provide backside openings.

公开(公告)号：US20190139973A1

公开(公告)日：2019-05-09

申请号：US15804692

申请日：2017-11-06

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Adarsh Rajashekhar

IPC: H01L27/11556 ,  H01L27/11582 ,  H01L21/8239 ,  H01L21/8234

Abstract: A memory opening is formed through an alternating stack of insulating layers and sacrificial material layers located over a substrate. Annular recesses are formed around the memory opening by laterally recessing the sacrificial material layers with respect to the insulating layers. Annular metal portions are formed over recessed sidewalls of the sacrificial material layers within each of the annular recesses by a selective deposition process. Annular backside blocking dielectrics are formed selectively on inner sidewalls of the annular metal portions employing a layer of a self-assembly material that covers surfaces of the insulating layers and inhibits deposition of a dielectric material thereupon. A memory stack structure is formed in the memory opening, and the sacrificial material layers are replaced with electrically conductive layers. The annular backside blocking dielectrics provide electrical isolation for the annular metal portions, which function as control gate electrodes.

公开(公告)号：US20180090373A1

公开(公告)日：2018-03-29

申请号：US15830838

申请日：2017-12-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar ,  Senaka Krishna Kanakamedala ,  Fumitaka Amano ,  Genta Mizuno

IPC: H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L21/285

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.

公开(公告)号：US12137554B2

公开(公告)日：2024-11-05

申请号：US17525233

申请日：2021-11-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou

IPC: H10B41/27 ,  H01L21/768 ,  H10B43/27

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory stack structures vertically extending through the alternating stack, etch stop plates located in the staircase region, laterally and vertically spaced apart among one another, and overlying an end portion of a respective one of the electrically conductive layers, and contact via structures located in a staircase region, vertically extending through a respective one of the etch stop plates, and contacting a respective one of the electrically conductive layers.