公开(公告)号：US10529620B2

公开(公告)日：2020-01-07

申请号：US15830838

申请日：2017-12-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar ,  Senaka Krishna Kanakamedala ,  Fumitaka Amano ,  Genta Mizuno

IPC: H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L27/11524 ,  H01L21/28 ,  H01L21/285

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.

公开(公告)号：US11894298B2

公开(公告)日：2024-02-06

申请号：US17655827

申请日：2022-03-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Naohiro Hosoda ,  Shuichi Hamaguchi ,  Kazuki Isozumi ,  Genta Mizuno ,  Yusuke Mukae ,  Ryo Nakamura ,  Yu Ueda

IPC: H01L23/522 ,  H01L23/532 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

CPC classification number: H01L23/5226 ,  H01L23/53223 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.

公开(公告)号：US11532570B2

公开(公告)日：2022-12-20

申请号：US17174064

申请日：2021-02-11

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Genta Mizuno ,  Kenzo Iizuka ,  Satoshi Shimizu ,  Keisuke Izumi ,  Tatsuya Hinoue ,  Yujin Terasawa ,  Seiji Shimabukuro ,  Ryousuke Itou ,  Yanli Zhang ,  Johann Alsmeier ,  Yusuke Yoshida

IPC: H01L27/11556 ,  H01L23/00 ,  H01L27/11582 ,  H01L23/522

Abstract: A three-dimensional memory device includes a first word-line region including a first alternating stack of first word lines and continuous insulating layers, first memory stack structures vertically extending through the first alternating stack, a second word-line region comprising a second alternating stack of second word lines and the continuous insulating layers, second memory stack structures vertically extending through the second alternating stack, plural dielectric separator structures located between the first word-line region and the second word-line region, and at least one bridge region located between the plural dielectric separator structures and between the between the first word-line region and the second word-line region. The continuous insulating layers extend through the at least one bridge region between the first alternating stack in the first word-line region and the second alternating stack in the second word-line region.

公开(公告)号：US11437270B2

公开(公告)日：2022-09-06

申请号：US16688290

申请日：2019-11-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar ,  Senaka Krishna Kanakamedala ,  Fumitaka Amano ,  Genta Mizuno

IPC: H01L27/11524 ,  H01L21/768 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L21/285 ,  H01L27/11575

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.

公开(公告)号：US11923321B2

公开(公告)日：2024-03-05

申请号：US17574182

申请日：2022-01-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shin Sakiyama ,  Genta Mizuno ,  Kenzo Iizuka ,  Takayuki Yokoyama ,  Toshiyuki Sega

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18 ,  H10B41/27 ,  H10B43/27

CPC classification number: H01L23/562 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H10B41/27 ,  H10B43/27 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/3511

Abstract: A memory die includes dielectric isolation rails embedded within a substrate semiconductor layer, laterally spaced apart along a first horizontal direction, and each laterally extending along a second horizontal direction that is perpendicular to the first horizontal direction, and alternating stacks of insulating layers and electrically conductive layers located over the substrate semiconductor layer. The alternating stacks are laterally spaced apart along the second horizontal direction by line trenches that laterally extend along the first horizontal direction. Arrays of memory stack structures are provided such that each array of memory stack structures among the arrays of memory stack structures vertically extends through a respective alternating stack. Each of the memory stack structures includes a respective vertical stack of memory elements and a respective vertical semiconductor channel.

公开(公告)号：US20180090373A1

公开(公告)日：2018-03-29

申请号：US15830838

申请日：2017-12-04

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar ,  Senaka Krishna Kanakamedala ,  Fumitaka Amano ,  Genta Mizuno

IPC: H01L21/768 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L27/11565 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/28 ,  H01L21/285

Abstract: A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.

公开(公告)号：US11289416B2

公开(公告)日：2022-03-29

申请号：US16695775

申请日：2019-11-26

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Masanori Tsutsumi ,  Naohiro Hosoda ,  Shuichi Hamaguchi ,  Kazuki Isozumi ,  Genta Mizuno ,  Yusuke Mukae ,  Ryo Nakamura ,  Yu Ueda

IPC: H01L29/76 ,  H01L23/522 ,  H01L23/532 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack, memory opening fill structures located in the memory openings, where each of the memory opening fill structures contains a memory film and a vertical semiconductor channel that extend vertically, and each memory film includes a crystalline blocking dielectric metal oxide layer, and a metal oxide amorphous dielectric nucleation layer located between each of the vertically neighboring electrically conductive layers and insulating layers, and located between each of the crystalline blocking dielectric metal oxide layers and each of the electrically conductive layers.

公开(公告)号：US10861869B2

公开(公告)日：2020-12-08

申请号：US16242245

申请日：2019-01-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ryo Nakamura ,  Yu Ueda ,  Tatsuya Hinoue ,  Shigehisa Inoue ,  Genta Mizuno ,  Masanori Tsutsumi

IPC: H01L27/11582 ,  H01L21/28 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11573 ,  H01L27/11565 ,  H01L27/1157

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Each of the memory stack structures includes respective charge storage elements and a respective vertical semiconductor channel contacting an inner sidewall of the respective charge storage elements. The sacrificial material layers are replaced with electrically conductive layers. A polycrystalline aluminum oxide blocking dielectric layer is provided between each charge storage element and a neighboring one of the electrically conductive layers. The polycrystalline aluminum oxide blocking dielectric layer is formed by: depositing an amorphous aluminum oxide layer, converting the amorphous aluminum oxide layer into an in-process polycrystalline aluminum oxide blocking dielectric layer, and by thinning the in-process polycrystalline aluminum oxide blocking dielectric layer.

公开(公告)号：US10381372B2

公开(公告)日：2019-08-13

申请号：US15332429

申请日：2016-10-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumitaka Amano ,  Takashi Arai ,  Genta Mizuno ,  Shigehisa Inoue ,  Naoki Takeguchi ,  Takashi Hamaya

IPC: H01L29/423 ,  H01L27/11582 ,  H01L21/768 ,  H01L27/11565 ,  H01L27/1157 ,  H01L21/285 ,  H01L23/532

Abstract: Void formation in tungsten lines in a three-dimensional memory device can be prevented by providing polycrystalline aluminum oxide liners in portions of lateral recesses that are laterally spaced from backside trenches by a distance grater than a predefined lateral offset distance. Tungsten nucleates on the polycrystalline aluminum oxide liners prior to nucleating on a metallic liner layer. Thus, tungsten layers can be deposited from the center portion of each backside recess, and the growth of tungsten can proceed toward the backside trenches. By forming the tungsten layers without voids, structural integrity of the three-dimensional memory device can be enhanced.

公开(公告)号：US10608010B2

公开(公告)日：2020-03-31

申请号：US16002265

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yujin Terasawa ,  Genta Mizuno ,  Yusuke Mukae ,  Yoshinobu Tanaka ,  Shiori Kataoka ,  Ryosuke Itou ,  Kensuke Yamaguchi ,  Naoki Takeguchi

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573

Abstract: An alternating stack of insulating layers and sacrificial material layers is formed with stepped surfaces. Sacrificial metal plates are formed on the top surfaces of the sacrificial material layers, and a retro-stepped dielectric material portion is formed over the sacrificial metal plates. Contact via cavities are formed through the retro-stepped dielectric material portion employing the sacrificial metal plates as etch stop structures. The sacrificial metal plates are replaced with portions of insulating spacer layers. Sacrificial via fill structures within remaining volumes of the contact via cavities. The sacrificial material layers are replaced with electrically conductive layers. The sacrificial via fill structures are replaced with portions of staircase-region contact via structures that contact the electrically conductive layers.