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公开(公告)号：US11968834B2
公开(公告)日：2024-04-23
申请号：US17192463
申请日：2021-03-04
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, memory openings vertically extending through the alternating stack and having lateral protrusions at levels of the electrically conductive layers, and memory opening fill structures located in the memory openings. Each of the memory opening fill structures includes a vertical semiconductor channel, a dielectric material liner laterally surrounding the vertical semiconductor channel, and a vertical stack of discrete memory elements laterally surrounding the dielectric material liner and located within volumes of the lateral protrusions. Each discrete memory element includes a vertical inner sidewall and a convex or stepped outer sidewall.
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公开(公告)号：US11594490B2
公开(公告)日：2023-02-28
申请号：US17155541
申请日：2021-01-22
发明人： Rahul Sharangpani , Raghuveer S. Makala , Fei Zhou
IPC分类号： H01L23/532 , H01L23/522 , H01L27/11556 , H01L21/768 , H01L27/11582
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a respective vertical semiconductor channel and a respective vertical stack of memory elements located at levels of the electrically conductive layers. Each of the electrically conductive layers includes a respective conductive liner comprising molybdenum carbide or carbonitride, and a respective molybdenum metal fill material portion.
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3.发明授权公开(公告)号：US11569260B2
公开(公告)日：2023-01-31
申请号：US17001003
申请日：2020-08-24
IPC分类号： H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11543 , H01L27/11556 , H01L27/11524 , H01L27/11519
摘要： A memory device includes an alternating stack of insulating layers, dielectric barrier liners and electrically conductive layers located over a substrate and a memory stack structure extending through each layer in the alternating stack. Each of the dielectric barrier liners is located between vertically neighboring pairs of an insulating layer and an electrically conductive layer within the alternating stack. The memory stack structure includes a memory film and a vertical semiconductor channel, the memory film includes a tunneling dielectric layer and a vertical stack of discrete memory-level structures that are vertically spaced from each other without direct contact between them, and each of the discrete memory-level structures includes a lateral stack including, from one side to another, a charge storage material portion, a silicon oxide blocking dielectric portion, and a dielectric metal oxide blocking dielectric portion.
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公开(公告)号：US11450687B2
公开(公告)日：2022-09-20
申请号：US17122360
申请日：2020-12-15
发明人： Roshan Tirukkonda , Ramy Nashed Bassely Said , Senaka Kanakamedala , Rahul Sharangpani , Raghuveer S. Makala , Adarsh Rajashekhar , Fei Zhou
IPC分类号： H01L27/11597 , H01L27/1159 , H01L27/11587 , H01L27/11585 , H01L27/11578
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers and memory stack structures vertically extending through the alternating stack. Each of the memory stack structures includes a vertical semiconductor channel and a vertical stack of ferroelectric memory elements surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers. Each of the ferroelectric memory elements includes a respective vertical stack of a first ferroelectric material portion and a second ferroelectric material portion that differs from the first ferroelectric material portion by at least one of a material composition and a lateral thickness.
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公开(公告)号：US11437270B2
公开(公告)日：2022-09-06
申请号：US16688290
申请日：2019-11-19
发明人： Rahul Sharangpani , Raghuveer S. Makala , Fei Zhou , Adarsh Rajashekhar , Senaka Krishna Kanakamedala , Fumitaka Amano , Genta Mizuno
IPC分类号： H01L27/11524 , H01L21/768 , H01L27/11556 , H01L27/11529 , H01L27/11519 , H01L27/1157 , H01L27/11582 , H01L27/11573 , H01L27/11565 , H01L23/532 , H01L23/528 , H01L23/522 , H01L21/28 , H01L21/285 , H01L27/11575
摘要： A method of forming a memory device includes forming an alternating stack of insulating layers and sacrificial material layers over a substrate forming memory stack structures through the alternating stack, forming a first backside trench and a second backside trench through the alternating stack, forming backside recesses by removing the sacrificial material layers, depositing a backside blocking dielectric layer after formation of the backside recesses, forming a liner that a lesser lateral extent than a lateral distance between the first backside trench and the second backside trench; and selectively growing a metal from surfaces of the liners while either not growing or growing at a lower rate the metal from surfaces of the backside recesses that are not covered by the liners.
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公开(公告)号：US11424265B2
公开(公告)日：2022-08-23
申请号：US17004811
申请日：2020-08-27
IPC分类号： H01L21/00 , H01L27/11582 , H01L27/11573 , H01L27/11575 , H01L27/11565 , H01L27/1157
摘要： A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a substrate including a single crystalline substrate semiconductor material, and memory stack structures extending through the alternating stack and containing a respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die contains a peripheral circuitry.
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公开(公告)号：US11424231B2
公开(公告)日：2022-08-23
申请号：US16917526
申请日：2020-06-30
IPC分类号： H01L21/00 , H01L25/18 , H01L29/16 , H01L27/11556 , H01L27/11529 , H01L27/11582 , H01L27/11573 , H01L25/065 , H01L25/00 , H01L23/00 , H01L29/04
摘要： A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.
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公开(公告)号：US11296028B2
公开(公告)日：2022-04-05
申请号：US16722824
申请日：2019-12-20
发明人： Ramy Nashed Bassely Said , Senaka Kanakamedala , Fei Zhou , Raghuveer S. Makala , Yao-Sheng Lee
IPC分类号： H01L23/522 , H01L23/532 , H01L23/528 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L27/11519 , H01L27/11524 , H01L27/11565
摘要： A structure, such as a semiconductor device, includes metal line structures located over a substrate and laterally spaced apart from each other. Each of the metal line structures includes planar metallic liner including a first metal element and a metal line body portion includes a second metal element that is different from the first metal element. Metal-organic framework (MOF) material portions are located between neighboring pairs of the metal line structures and contain metal ions or clusters of the first metal element and organic ligands connected to the metal ions or clusters of the first metal element. Air gaps may be formed in the MOF material portions to further reduce the effective dielectric constant.
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公开(公告)号：US20210397170A1
公开(公告)日：2021-12-23
申请号：US17465305
申请日：2021-09-02
发明人： Fei Zhou , Cheng-Chung Chu , Raghuveer Makala
IPC分类号： G05B19/418 , G05B13/02 , H01L21/66
摘要： Techniques are presented for the application of neural networks to the fabrication of integrated circuits and electronic devices, where example are given for the fabrication of non-volatile memory circuits and the mounting of circuit components on the printed circuit board of a solid state drive (SSD). The techniques include the generation of high precision masks suitable for analyzing electron microscope images of feature of integrated circuits and of handling the training of the neural network when the available training data set is sparse through use of a generative adversary network (GAN).
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10.发明授权公开(公告)号：US11201139B2
公开(公告)日：2021-12-14
申请号：US16825304
申请日：2020-03-20
IPC分类号： H01L25/065 , H01L23/00 , H01L25/00 , H01L25/18
摘要： A first semiconductor die includes first semiconductor devices located over a first substrate, first interconnect-level dielectric material layers embedding first metal interconnect structures and located on the first semiconductor devices, and a first pad-level dielectric layer located on the first interconnect-level dielectric material layers and embedding first bonding pads. Each of the first bonding pads includes a first proximal horizontal surface and at least one first distal horizontal surface that is more distal from the first substrate than the first proximal horizontal surface is from the first substrate and has a lesser total area than a total area of the first proximal horizontal surface. A second semiconductor die including second bonding pads that are embedded in a second pad-level dielectric layer can be bonded to a respective distal surface of the first bonding pads.
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