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公开(公告)号：US11972954B2
公开(公告)日：2024-04-30
申请号：US17355955
申请日：2021-06-23
发明人： Roshan Jayakhar Tirukkonda , Senaka Kanakamedala , Rahul Sharangpani , Raghuveer S. Makala , Monica Titus
IPC分类号： H01L21/311 , H01L21/768 , H01L23/535 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40 , H10B51/20 , H10B51/40
CPC分类号： H01L21/31144 , H01L21/31116 , H01L21/76805 , H01L21/76877 , H01L23/535 , H10B41/27 , H10B41/41 , H10B43/27 , H10B43/40 , H10B51/20 , H10B51/40
摘要： An alternating stack of first material layers and second material layers can be formed over a semiconductor material layer. A patterning film is formed over the alternating stack, and openings are formed through the patterning film. Via openings are formed through the alternating stack at least to a top surface of the semiconductor material layer by performing a first anisotropic etch process that transfers a pattern of the openings in the patterning film. A cladding liner can be formed on a top surface of the patterning film and sidewalls of the openings in the pattering film. The via openings can be vertically extended through the semiconductor material layer at least to a bottom surface of the semiconductor material layer by performing a second anisotropic etch process employing the cladding liner as an etch mask.
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公开(公告)号：US11631695B2
公开(公告)日：2023-04-18
申请号：US17085735
申请日：2020-10-30
IPC分类号： H01L23/522 , H01L27/11582 , H01L27/11556 , G11C8/14 , H01L27/1157 , H01L27/11519 , H01L27/11524 , H01L27/11565
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate. Each electrically conductive layer within a subset of the electrically conductive layers includes a respective first metal layer containing an elemental metal and a respective first metal silicide layer containing a metal silicide of the elemental metal. Memory openings vertically extend through the alternating stack. Memory opening fill structures located within the memory openings can include a respective memory film and a respective vertical semiconductor channel.
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公开(公告)号：US11594553B2
公开(公告)日：2023-02-28
申请号：US17150561
申请日：2021-01-15
IPC分类号： H01L27/11597 , H01L27/1159 , H01L27/11587 , H01L27/11563 , H01L27/11578 , H01L27/11582
摘要： A ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and containing a vertical stack of memory elements and a vertical semiconductor channel. Each memory element within the vertical stack of memory elements includes a crystalline ferroelectric memory material portion and an epitaxial template portion.
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公开(公告)号：US11521984B2
公开(公告)日：2022-12-06
申请号：US16910752
申请日：2020-06-24
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11556 , H01L27/11524 , H01L27/11519 , H01L27/11565
摘要： A source-level sacrificial layer and an alternating stack of insulating layers and spacer material layers are formed over a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory openings are formed through the alternating stack and the source-level sacrificial layer, and memory opening fill structures are formed. A source cavity is formed by removing the source-level sacrificial layer, and exposing an outer sidewall of each vertical semiconductor channel in the memory opening fill structures. A metal-containing layer is deposited on physically exposed surfaces of the vertical semiconductor channel and the vertical semiconductor channel is crystallized using metal-induced lateral crystallization. Alternatively or additionally, cylindrical metal-semiconductor alloy regions can be formed around the vertical semiconductor channels to reduce contact resistance. A source contact layer can be formed in the source cavity.
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公开(公告)号：US11244958B2
公开(公告)日：2022-02-08
申请号：US16888014
申请日：2020-05-29
发明人： Zhixin Cui , Fei Zhou , Raghuveer S. Makala
IPC分类号： H01L27/11582 , H01L21/3105 , H01L27/1157 , H01L27/11524 , H01L23/528 , H01L23/532 , H01L29/08 , H01L23/522 , H01L21/02 , H01L21/768 , H01L21/3213 , H01L21/311 , H01L27/11556
摘要： An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory stack structures are formed through the alternating stack. Drain-select-level trenches through an upper subset of the sacrificial material layers, and backside trenches are formed through each layer of the alternating stack. Backside recesses are formed by removing the sacrificial material layers. A first electrically conductive material and a second electrically conductive material are sequentially deposited in the backside recesses and the drain-select-level trenches. Portions of the second electrically conductive material and the first electrically conductive material may be removed by at least one anisotropic etch process from the drain-select-level trenches to provide drain-select-level electrically conductive layers as multiple groups that are laterally spaced apart and electrically isolated from one another by cavities within the drain-select-level trenches.
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公开(公告)号：US11239253B2
公开(公告)日：2022-02-01
申请号：US16917597
申请日：2020-06-30
IPC分类号： H01L21/00 , H01L27/11582 , H01L27/11565 , H01L27/1157 , H01L27/11556 , H01L27/11519 , H01L27/11524 , H01L27/11543 , H01L27/11573
摘要： A semiconductor structure includes a memory die bonded to a support die. The memory die includes an alternating stack of insulating layers and electrically conductive layers located over a first single crystalline semiconductor layer, and memory stack structures extending through the alternating stack and containing respective memory film and a respective vertical semiconductor channel including a single crystalline channel semiconductor material. The support die includes a peripheral circuitry.
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公开(公告)号：US11121140B2
公开(公告)日：2021-09-14
申请号：US16737088
申请日：2020-01-08
IPC分类号： H01L47/00 , H01L27/11514 , H01L49/02 , H01L27/11504 , H01L45/00 , H01L23/528
摘要： A ferroelectric tunnel junction memory device includes a bit line, a word line and a memory cell located between the bit line and the word line. The memory cell includes a ferroelectric tunneling dielectric portion and an ovonic threshold switch material portion.
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公开(公告)号：US11049880B2
公开(公告)日：2021-06-29
申请号：US16530256
申请日：2019-08-02
IPC分类号： H01L27/11597 , H01L27/1157 , H01L27/11582 , H01L27/11587 , H01L27/11565 , H01L27/11519 , H01L27/11524 , H01L27/11556 , H01L27/1159
摘要： A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures includes a vertical stack of single crystalline ferroelectric dielectric layers and a respective vertical semiconductor channel.
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公开(公告)号：US10998331B2
公开(公告)日：2021-05-04
申请号：US16020505
申请日：2018-06-27
发明人： Fei Zhou , Yingda Dong , Raghuveer S. Makala
IPC分类号： H01L27/11582 , H01L27/1157 , H01L27/11565 , H01L21/311 , H01L21/28
摘要： A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by line trenches. The line trenches laterally extend along a first horizontal direction and are spaced apart along a second horizontal direction. Each line trench fill structure includes a laterally undulating dielectric rail having a laterally undulating width along the second horizontal direction and extending along the first horizontal direction and a row of memory stack structures located at neck regions of the laterally undulating dielectric rail. Each memory stack structure includes a vertical semiconductor channel, a blocking dielectric contacting an outer sidewall of the vertical semiconductor channel, and a charge storage layer contacting an outer sidewall of the blocking dielectric, vertically extending continuously through each level of the electrically conductive strips, and having a vertically undulating lateral thickness.
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10.发明授权公开(公告)号：US10950629B2
公开(公告)日：2021-03-16
申请号：US16877535
申请日：2020-05-19
IPC分类号： H01L27/11582 , H01L21/02 , H01L27/1157 , H01L27/11529 , H01L27/11524 , H01L27/11565 , H01L27/11578 , H01L21/28 , H01L27/11556
摘要： A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips laterally spaced apart by line trenches, and an alternating two-dimensional array of memory stack assemblies and dielectric pillar structures located in the line trenches. Each of the line trenches is filled with a respective laterally alternating sequence of memory stack assemblies and dielectric pillar structures. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory film. The vertical semiconductor channel includes a semiconductor channel layer having large grains, which can be provided by a selective semiconductor growth from seed semiconductor material layers, sacrificial semiconductor material layers, or a single crystalline semiconductor material in a semiconductor substrate underlying the alternating stacks.
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