公开(公告)号：US11758730B2

公开(公告)日：2023-09-12

申请号：US17315938

申请日：2021-05-10

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fumiaki Toyama ,  Jee-Yeon Kim

IPC: H01L25/065 ,  H10B43/40 ,  G11C11/408 ,  H10B43/27

CPC classification number: H10B43/40 ,  G11C11/4085 ,  H01L25/0657 ,  H10B43/27 ,  H01L2225/06541

Abstract: A bonded assembly of a memory die and a logic die is provided. The memory die includes a memory array, a plurality of bit lines, and memory-side bit-line-connection bonding pads. The logic die includes sense amplifiers located in a sense amplifier region, and logic-side bit-line-connection bonding pads located within the sense amplifier region and bonded to a respective one of the memory-side bit-line-connection bonding pads. The sense amplifier region has an areal overlap with a respective first subset the plurality of bit lines in a plan view, while a second subset of the plurality of bit lines does not have an areal overlap with the sense amplifier region in the plan view.

公开(公告)号：US11011209B2

公开(公告)日：2021-05-18

申请号：US16589404

申请日：2019-10-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jee-Yeon Kim ,  Kwang-Ho Kim ,  Yuki Mizutani ,  Fumiaki Toyama

IPC: H01L29/76 ,  G11C5/06 ,  H01L23/522 ,  H01L23/528 ,  H01L23/00 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519

Abstract: A semiconductor structure includes a memory die, which includes an alternating stack of insulating layers and electrically conductive layers located over a substrate and memory stack structures vertically extending through the alternating stacks. A contact-level dielectric layer embeds drain contact via structures that are electrically connected to a respective drain region and contact-level metal interconnects, and a via-level dielectric embedding drain-to-bit-line connection via structures, bit-line-connection via structures, and pad-connection via structures. A bit-line-level dielectric layer overlies the via-level dielectric layer, and embeds bit lines that contact a respective subset of the drain-to-bit-line connection via structures, and embeds metal pads that contact a respective one of the pad-connection via structures. Each metal pad is electrically connected to a respective bit line through a series connection of a respective pad-connection via structure, a respective contact-level metal interconnect, and a respective bit-line-connection via structure.

公开(公告)号：US11342244B2

公开(公告)日：2022-05-24

申请号：US16747943

申请日：2020-01-21

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jee-Yeon Kim ,  Kwang-Ho Kim ,  Fumiaki Toyama

IPC: H01L23/48 ,  H01L25/065 ,  H01L21/768 ,  H01L23/00

Abstract: Through-substrate via structures are formed in a semiconductor substrate of a first semiconductor die. Semiconductor devices, dielectric material layers, and metal interconnect structures are formed over a front surface of the semiconductor substrate. A backside dielectric layer is formed on a backside surface. Integrated line and pad structures are formed over the backside dielectric layer on a respective through-substrate via structure. Each of the integrated line and pad structures includes a respective pad portion and respective line portion that extends from a center region of the backside surface to toward a periphery of the backside surface. A bonded assembly including the first semiconductor die and a second semiconductor die can be formed. Bonding pads can be provided in a center region of the interface between the semiconductor dies to facilitate power and signal distribution in the second semiconductor die with less electrical wiring.

公开(公告)号：US11211370B2

公开(公告)日：2021-12-28

申请号：US16774372

申请日：2020-01-28

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jee-Yeon Kim ,  Yuki Mizutani ,  Fumiaki Toyama

IPC: H01L25/18 ,  H01L23/48 ,  H01L25/00 ,  H01L27/06

Abstract: A bonded assembly includes a memory die containing a memory device and a plurality of bit lines, and logic die bonded to the memory die. The logic die contains a control circuit configured to control operation of the memory device. The control circuit contains a peripheral circuit region, a sense amplifier region, and a power and control signal region located adjacent to the sense amplifier region and containing at least one power and control signal interconnect structure which is configured to provide a power or control signal to or from the peripheral circuit region.

公开(公告)号：US10861873B2

公开(公告)日：2020-12-08

申请号：US16404844

申请日：2019-05-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jee-Yeon Kim ,  Kwang-Ho Kim ,  Fumiaki Toyama

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11573 ,  H01L27/11529 ,  G11C5/06 ,  H01L27/11556 ,  H01L27/11558 ,  H01L27/11565 ,  H01L27/1157

Abstract: A three-dimensional memory device includes a plurality of alternating stacks of insulating layers and electrically conductive layers located over a substrate, clusters of memory stack structures vertically extending through a respective one of the alternating stacks, and bit lines electrically connected to an upper end of a respective subset of the vertical semiconductor channels. In one embodiment, a subset of the bit lines can include a respective multi-level structure. Each multi-level structure includes bit-line-level bit line segments and an interconnection line segment located at a different level from the bit-line-level bit line segments. In another embodiment, groups of alternating stacks can be alternately indented along a horizontal direction perpendicular to the bit lines to provide dielectric material portions located in lateral indentation regions. Metal line structures connecting contact via structures can extend parallel to bit lines to provide electrical connections between word lines and underlying field effect transistors.

公开(公告)号：US11139237B2

公开(公告)日：2021-10-05

申请号：US16547971

申请日：2019-08-22

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Shiqian Shao ,  Jee-Yeon Kim ,  Fumiaki Toyama ,  Hirofumi Tokita

IPC: H01L27/115 ,  H01L23/522 ,  G11C5/06 ,  H01L23/528 ,  H01L27/11519 ,  H01L27/11582 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11524

Abstract: A method of forming a three-dimensional memory device includes forming a vertically alternating sequence of insulating layers and spacer material layers over a substrate, where the spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers, forming multiple sets of stepped surfaces in terrace regions of the vertically alternating sequence, forming memory stack structures through memory array regions of the vertically alternating sequence, and forming a metal interconnect structure which electrically connects a portion of a topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region, and which extends above a horizontal plane of the topmost electrically conductive layer in the first memory array region and a portion of a topmost electrically conductive layer in the second memory array region.