公开(公告)号：US11121140B2

公开(公告)日：2021-09-14

申请号：US16737088

申请日：2020-01-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Seung-Yeul Yang ,  Raghuveer S. Makala ,  Fei Zhou ,  Adarsh Rajashekhar ,  Rahul Sharangpani

IPC: H01L47/00 ,  H01L27/11514 ,  H01L49/02 ,  H01L27/11504 ,  H01L45/00 ,  H01L23/528

Abstract: A ferroelectric tunnel junction memory device includes a bit line, a word line and a memory cell located between the bit line and the word line. The memory cell includes a ferroelectric tunneling dielectric portion and an ovonic threshold switch material portion.

公开(公告)号：US10381559B1

公开(公告)日：2019-08-13

申请号：US16002169

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Christopher J. Petti ,  Rahul Sharangpani ,  Adarsh Rajashekhar ,  Seung-Yeul Yang

IPC: G11C13/00 ,  H01L27/24 ,  H01L45/00

Abstract: Alternating stacks of insulating strips and sacrificial material strips are formed over a substrate. A laterally alternating sequence of pillar cavities and pillar structures can be formed within each of the line trenches. A phase change memory cell including a discrete metal portion, a phase change memory material portion, and a selector material portion is formed at each level of the sacrificial material strips at a periphery of each of the pillar cavities. Vertical bit lines are formed in the two-dimensional array of pillar cavities. Remaining portions of the sacrificial material strips are replaced with electrically conductive word line strips. Pathways for providing an isotropic etchant for the sacrificial material strips and a reactant for a conductive material of the electrically conductive word line strips may be provided by a backside trench, or by removing the pillar structures to provide backside openings.

公开(公告)号：US11239254B2

公开(公告)日：2022-02-01

申请号：US16910638

申请日：2020-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou ,  Seung-Yeul Yang

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel, a vertical stack of majority germanium layers each containing at least 51 atomic percent germanium, and a vertical stack of ferroelectric dielectric layers.

公开(公告)号：US10937809B1

公开(公告)日：2021-03-02

申请号：US16541289

申请日：2019-08-15

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Raghuveer S. Makala ,  Seung-Yeul Yang ,  Fei Zhou ,  Adarsh Rajashekhar

IPC: H01L27/11597 ,  G11C11/22 ,  H01L27/11592 ,  H01L27/1159 ,  H01L27/11587

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a respective transition metal nitride liner and a respective conductive fill material layer, a vertical semiconductor channel vertically extending through the alternating stack, a vertical stack of transition metal nitride spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and discrete ferroelectric material portions laterally surrounding the respective transition metal nitride spacers and located at the levels of the electrically conductive layers.

公开(公告)号：US10381409B1

公开(公告)日：2019-08-13

申请号：US16002243

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Fei Zhou ,  Raghuveer S. Makala ,  Christopher J. Petti ,  Rahul Sharangpani ,  Adarsh Rajashekhar ,  Seung-Yeul Yang

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

Abstract: Alternating stacks of insulating strips and sacrificial material strips are formed over a substrate. A laterally alternating sequence of pillar cavities and pillar structures can be formed within each of the line trenches. A phase change memory cell including a discrete metal portion, a phase change memory material portion, and a selector material portion is formed at each level of the sacrificial material strips at a periphery of each of the pillar cavities. Vertical bit lines are formed in the two-dimensional array of pillar cavities. Remaining portions of the sacrificial material strips are replaced with electrically conductive word line strips. Pathways for providing an isotropic etchant for the sacrificial material strips and a reactant for a conductive material of the electrically conductive word line strips may be provided by a backside trench, or by removing the pillar structures to provide backside openings.

公开(公告)号：US11545506B2

公开(公告)日：2023-01-03

申请号：US17097757

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati Prasad ,  Joyeeta Nag ,  Seung-Yeul Yang ,  Adarsh Rajashekhar ,  Raghuveer S. Makala

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L29/66 ,  H01L29/51 ,  H01L27/1159

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US11996462B2

公开(公告)日：2024-05-28

申请号：US17097841

申请日：2020-11-13

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Bhagwati Prasad ,  Joyeeta Nag ,  Seung-Yeul Yang ,  Adarsh Rajashekhar ,  Raghuveer S. Makala

IPC: H01L29/51 ,  H01L21/28 ,  H01L21/3115 ,  H01L29/66 ,  H01L29/78 ,  H10B51/20 ,  H10B51/30

CPC classification number: H01L29/516 ,  H01L21/31155 ,  H01L29/40111 ,  H01L29/6684 ,  H01L29/78391 ,  H10B51/20 ,  H10B51/30

Abstract: A ferroelectric transistor includes a semiconductor channel comprising a semiconductor material, a strained and/or defect containing ferroelectric gate dielectric layer located on a surface of the semiconductor channel, a source region located on a first end portion of the semiconductor channel, and a drain region located on a second end portion of the semiconductor channel.

公开(公告)号：US11302716B2

公开(公告)日：2022-04-12

申请号：US16876816

申请日：2020-05-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Raghuveer S. Makala ,  Yanli Zhang ,  Fei Zhou ,  Rahul Sharangpani ,  Adarsh Rajashekhar ,  Seung-Yeul Yang

IPC: H01L27/11597 ,  H01L27/11587 ,  H01L27/1159 ,  H01L27/11585 ,  H01L23/528 ,  H01L23/522

Abstract: A memory opening or a line trench is formed through an alternating stack of insulating layers and sacrificial material layers. A memory opening fill structure or a memory stack assembly is formed, which includes a vertical stack of discrete intermediate metallic electrodes formed on sidewalls of the sacrificial material layers, a gate dielectric layer, and a vertical semiconductor channel. Backside recesses are formed by removing the sacrificial material layers selective to the insulating layers, and a combination of a ferroelectric dielectric layer and an electrically conductive layer within each of the backside recesses. The electrically conductive layer is laterally spaced from a respective one of the discrete intermediate metallic electrodes by the ferroelectric dielectric layer. Ferroelectric-metal-insulator memory elements are formed around the vertical semiconductor channel.

公开(公告)号：US20210036019A1

公开(公告)日：2021-02-04

申请号：US16910638

申请日：2020-06-24

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Rahul Sharangpani ,  Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Fei Zhou ,  Seung-Yeul Yang

IPC: H01L27/11597 ,  H01L27/11587

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and a memory stack structure extending through the alternating stack. The memory stack structure includes a vertical semiconductor channel, a vertical stack of majority germanium layers each containing at least 51 atomic percent germanium, and a vertical stack of ferroelectric dielectric layers.

公开(公告)号：US11309332B2

公开(公告)日：2022-04-19

申请号：US16568668

申请日：2019-09-12

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Adarsh Rajashekhar ,  Raghuveer S. Makala ,  Rahul Sharangpani ,  Seung-Yeul Yang ,  Fei Zhou

IPC: H01L27/11582 ,  H01L27/1157 ,  H01L27/11597 ,  H01L27/1159 ,  H01L27/11587

Abstract: A three-dimensional ferroelectric memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where each of the electrically conductive layers contains a transition metal element-containing conductive liner and a conductive fill material portion, a vertical semiconductor channel extending vertically through the alternating stack, a vertical stack of tubular transition metal element-containing conductive spacers laterally surrounding the vertical semiconductor channel and located at levels of the electrically conductive layers, and a ferroelectric material layer located between the vertical stack of tubular transition metal element-containing conductive spacers and the transition metal element-containing conductive liner.