公开(公告)号：US12004356B2

公开(公告)日：2024-06-04

申请号：US17654762

申请日：2022-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lei Wan ,  Jordan Katine ,  Tsai-Wei Wu

IPC: G11C11/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/10 ,  H10N50/01 ,  H10N50/80

Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.

公开(公告)号：US12004357B2

公开(公告)日：2024-06-04

申请号：US17654768

申请日：2022-03-14

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Lei Wan ,  Jordan Katine ,  Tsai-Wei Wu ,  Chu-Chen Fu

IPC: G11C11/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/10 ,  H10N50/01 ,  H10N50/80

Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.

公开(公告)号：US20210313392A1

公开(公告)日：2021-10-07

申请号：US17354541

申请日：2021-06-22

Applicant: SanDisk Technologies LLC

Inventor： Lei Wan ,  Tsai-Wei Wu ,  Jordan A. Katine

IPC: H01L27/22 ,  H01L43/12 ,  H01L27/24

Abstract: A memory array is provided that includes a plurality of word lines and a plurality of bit lines, and a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element. Each memory cell is coupled between one of the word lines and one of the bit lines. Each memory cell has a half-pitch F, and comprises an area between 2F2 and 4F2.

公开(公告)号：US11056534B2

公开(公告)日：2021-07-06

申请号：US16460820

申请日：2019-07-02

Applicant: SanDisk Technologies LLC

Inventor： Lei Wan ,  Tsai-Wei Wu ,  Jordan A. Katine

IPC: H01L27/22 ,  H01L43/12 ,  H01L27/24 ,  H01L43/10

Abstract: A memory array is provided that includes a first memory level having a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element, and a plurality of vias, each of the vias coupled in series with a corresponding one of the memory cells.

公开(公告)号：US11882706B2

公开(公告)日：2024-01-23

申请号：US17354541

申请日：2021-06-22

Applicant: SanDisk Technologies LLC

Inventor： Lei Wan ,  Tsai-Wei Wu ,  Jordan A. Katine

IPC: H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N52/85 ,  H10N52/01 ,  H10N50/85

CPC classification number: H10B61/10 ,  H10B61/00 ,  H10B63/20 ,  H10B63/24 ,  H10N50/01 ,  H10N52/01 ,  H10N52/85 ,  H10N50/85

Abstract: A memory array is provided that includes a plurality of word lines and a plurality of bit lines, and a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element. Each memory cell is coupled between one of the word lines and one of the bit lines. Each memory cell has a half-pitch F, and comprises an area between 2F2 and 4F2.