公开(公告)号：US20240365685A1

公开(公告)日：2024-10-31

申请号：US18771255

申请日：2024-07-12

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Shy-Jay LIN ,  Mingyuan SONG

IPC: H10N52/80 ,  H10B61/00 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

CPC classification number: H10N52/80 ,  H10B61/22 ,  H10N50/85 ,  H10N52/00 ,  H10N52/01

Abstract: A spin-orbit-torque (SOT) magnetic device includes a bottom metal layer, a first magnetic layer, as a magnetic free layer, disposed over the bottom metal layer, a spacer layer disposed over the first magnetic layer, and a second magnetic layer disposed over the spacer layer. The first magnetic layer includes a lower magnetic layer, a middle layer made of non-magnetic layer and an upper magnetic layer.

公开(公告)号：US12063873B2

公开(公告)日：2024-08-13

申请号：US18096762

申请日：2023-01-13

Applicant: TDK CORPORATION

Inventor： Shinto Ichikawa ,  Katsuyuki Nakada

IPC: H10N50/85 ,  H10N52/01 ,  H10N52/80

CPC classification number: H10N52/80 ,  H10N50/85 ,  H10N52/01

Abstract: A tunnel barrier layer includes a non-magnetic oxide, wherein a crystal structure of the tunnel barrier layer includes both an ordered spinel structure and a disordered spinel structure.

公开(公告)号：US12048166B2

公开(公告)日：2024-07-23

申请号：US17295529

申请日：2019-11-21

Applicant: LFOUNDRY S.R.L.

Inventor： Carsten Schmidt ,  Mario Blasini ,  Gerhard Spitzlsperger ,  Alessandro Montagna

IPC: H10B61/00 ,  G01R33/07 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H10N52/00 ,  H10N52/01 ,  H10N52/80 ,  H10N59/00

CPC classification number: H10B61/00 ,  G01R33/072 ,  G01R33/077 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L25/0657 ,  H10N52/01 ,  H10N52/101 ,  H10N52/80 ,  H10N59/00

Abstract: A Hall integrated circuit including a vertical Hall element, having a first wafer and a second wafer, the second wafer including a CMOS substrate integrating a CMOS processing circuit coupled to the vertical Hall element and a stack of dielectric layers, and the first wafer including a Hall-sensor layer having a first surface and a second surface, the first and second wafers being bonded with the interposition of a dielectric layer arranged above the first surface of the Hall-sensor layer. The vertical Hall element has: at least a first Hall terminal; at least a second Hall terminal; a deep trench isolation ring extending through the Hall-sensor layer from the first surface to the second surface and enclosing and isolating a Hall sensor region of the Hall-sensor layer; and a first and a second conductive structures electrically connected to respective contact pads embedded in the stack of the second wafer.

公开(公告)号：US20240210497A1

公开(公告)日：2024-06-27

申请号：US18146447

申请日：2022-12-26

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Daiki Komatsu ,  Masamitsu Matsuura

IPC: G01R33/07 ,  H10N52/00 ,  H10N52/01

CPC classification number: G01R33/077 ,  H10N52/01 ,  H10N52/101

Abstract: An integrated circuit (IC) package comprises a semiconductor die having a first surface with a Hall-effect sensor circuit and a second surface. A plurality of through substrate vias (TSV) each having a metal layer extend from the first surface of the semiconductor die to the second surface. The IC package includes a portion of a leadframe having a first set of leads and a second set of leads. The first set of leads provide a field generating current path for directing a magnetic field toward the Hall-effect sensor circuit. The second set of leads are attached to bond pads on the semiconductor die. A first side of an insulator is attached to the leadframe using a die attach material, and a second side of the insulator is attached to the first side of the semiconductor die using a bonding material.

公开(公告)号：US11917925B2

公开(公告)日：2024-02-27

申请号：US16750264

申请日：2020-01-23

Applicant: Everspin Technologies, Inc.

Inventor： Shimon

IPC: H01L43/00 ,  H10N50/85 ,  H10N52/80 ,  H10N52/00 ,  G11C11/16 ,  H10N52/01

CPC classification number: H10N52/101 ,  G11C11/161 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: The magnetoresistive stack or structure of a magnetoresistive device includes one or more electrodes or electrically conductive lines, a magnetically fixed region, a magnetically free region disposed between the electrodes or electrically conductive lines, and a dielectric layer disposed between the free and fixed regions. The magnetoresistive device may further include a spin-Hall (SH) material proximate to at least a portion of the free region, and one or more insertion layers comprising antiferromagnetic material.

公开(公告)号：US11899082B2

公开(公告)日：2024-02-13

申请号：US17015327

申请日：2020-09-09

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Keith Ryan Green ,  Tony Ray Larson

IPC: G01R33/07 ,  H10N52/80 ,  H10N52/00 ,  H10N52/01

CPC classification number: G01R33/072 ,  H10N52/101 ,  H10N52/80 ,  H10N52/01

Abstract: An integrated circuit includes a doped region having a first conductivity type formed in a semiconductor substrate having a second conductivity type. A dielectric layer is located between the doped region and a surface plane of the semiconductor substrate, and a polysilicon layer is located over the dielectric layer. First, second, third and fourth terminals are connected to the doped region, the first and third terminals defining a conductive path through the doped region and the second and fourth terminals defining a second conductive path through the doped region, the second path intersecting the first path.

公开(公告)号：US20240032443A1

公开(公告)日：2024-01-25

申请号：US18154986

申请日：2023-01-16

Applicant: Hyundai Motor Company ,  Kia Corporation ,  Korea Advanced Institute of Science and Technology

Inventor： Ji-Sung Lee ,  Joon-Hyun Kwon ,  Su-Jung Noh ,  Han-Saem Lee ,  Dae-Kyu Koh ,  Byong-Guk Park ,  Jaimin Kang ,  Soogil Lee

IPC: H10N52/80 ,  H10N52/85 ,  H10N52/01

CPC classification number: H10N52/80 ,  H10N52/85 ,  H10N52/01

Abstract: An embodiment magnetic memory device based on perpendicular exchange bias includes a non-magnetic layer, a ferromagnetic layer bonded on the non-magnetic layer, wherein a magnetization direction of the ferromagnetic layer is randomly distributed, and an anti-ferromagnetic layer bonded on the ferromagnetic layer. An embodiment method of manufacturing a magnetic memory device includes preparing the magnetic memory device based on perpendicular exchange bias, the preparing including bonding a ferromagnetic layer on a non-magnetic layer and bonding an anti-ferromagnetic layer on the ferromagnetic layer, and demagnetizing the ferromagnetic layer of the magnetic memory device, wherein a magnetization direction of the ferromagnetic layer is randomly distributed.

公开(公告)号：US11882706B2

公开(公告)日：2024-01-23

申请号：US17354541

申请日：2021-06-22

Applicant: SanDisk Technologies LLC

Inventor： Lei Wan ,  Tsai-Wei Wu ,  Jordan A. Katine

IPC: H10B61/00 ,  H10B63/00 ,  H10N50/01 ,  H10N52/85 ,  H10N52/01 ,  H10N50/85

CPC classification number: H10B61/10 ,  H10B61/00 ,  H10B63/20 ,  H10B63/24 ,  H10N50/01 ,  H10N52/01 ,  H10N52/85 ,  H10N50/85

Abstract: A memory array is provided that includes a plurality of word lines and a plurality of bit lines, and a plurality of memory cells each including a corresponding magnetic memory element coupled in series with a corresponding selector element. Each memory cell is coupled between one of the word lines and one of the bit lines. Each memory cell has a half-pitch F, and comprises an area between 2F2 and 4F2.

公开(公告)号：US11854589B2

公开(公告)日：2023-12-26

申请号：US17509014

申请日：2021-10-24

Applicant: Yimin Guo ,  Rongfu Xiao ,  Jun Chen

Inventor： Yimin Guo ,  Rongfu Xiao ,  Jun Chen

IPC: G11C11/00 ,  G11C11/16 ,  G11B5/39 ,  H01F10/32 ,  H10B61/00 ,  H10N50/10 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

CPC classification number: G11C11/161 ,  G11B5/3909 ,  G11C11/1675 ,  H01F10/3286 ,  H10B61/22 ,  H10N50/10 ,  H10N50/85 ,  H10N52/01 ,  H10N52/80

Abstract: A magnetoresistive element comprises a nonmagnetic sidewall-current-channel (SCC) structure provided on a surface of the SOT material layer that exhibits the Spin Hall Effect, which is opposite to a surface of the SOT material layer where the magnetic recording layer is provided, and comprising an insulating medium in a central region of the SCC structure, and a conductive medium being a sidewall of the SCC structure and surrounding the insulating medium, making an electric current crowding inside the SOT material layer and the magnetic recording layer to achieve a spin-orbit torque and a higher spin-polarization degree for an applied electric current.

公开(公告)号：US11844287B2

公开(公告)日：2023-12-12

申请号：US17145048

申请日：2021-01-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chien-Min Lee ,  Shy-Jay Lin

IPC: H01L43/00 ,  H10N52/80 ,  H01F41/30 ,  H01F10/32 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  H10N52/01 ,  H10N52/00

CPC classification number: H10N52/80 ,  H01F10/329 ,  H01F10/3254 ,  H01F10/3272 ,  H01F41/302 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85 ,  H10N52/01 ,  H10N52/101

Abstract: A magnetic memory device includes a spin-orbit torque (SOT) induction spin Hall electrode and a free layer of a magnetic tunnel junction (MTJ) stack disposed on the spin Hall electrode which is a synthetic anti-ferromagnetic structure. The free layer has a magnetic moment which is askew of the long axis of the MTJ stack and askew the direction of current flow through the spin Hall electrode. The MTJ stack internally generates a magnetic field to switch the state of the free layer. The free layer includes a first layer separated from a second layer by a spacer layer, where the first layer and the second layer may have the same or different crystalline structures.