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公开(公告)号:US20240324242A1
公开(公告)日:2024-09-26
申请号:US18605999
申请日:2024-03-15
Applicant: Kioxia Corporation
Inventor: Kazuya SAWADA , Toshihiko NAGASE , Kenichi YOSHINO , Hyungjun CHO , Naoki AKIYAMA , Takuya SHIMANO
Abstract: According to one embodiment, a memory device includes a first wiring line extending along a first direction, a second wiring line provided on an upper layer side of the first wiring line and extending along a second direction intersecting the first direction, and a memory cell provided between the first wiring line and the second wiring line, and including a magnetoresistance effect element, a switching element, a middle electrode provided between the magnetoresistance effect element and the switching element, and a resistive layer provided between the magnetoresistance effect element and the second wiring line. A resistance of the resistive layer is higher than a resistance of the middle electrode.
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公开(公告)号:US20240147735A1
公开(公告)日:2024-05-02
申请号:US18187151
申请日:2023-03-21
Applicant: Samsung Electronics Co., Ltd.
Inventor: Sung HEO , Hajun SUNG , Seongyong PARK , Wooyoung YANG , Dongjin YUN
Abstract: A switching device including a first electrode layer, a second electrode layer arranged to face the first electrode layer, and a selection layer arranged between the first electrode layer and the second electrode layer, wherein the first electrode layer is doped with at least one of manganese (Mn), iron (Fe), niobium (Nb), molybdenum (Mo), technetium (Tc), ruthenium (Ru), rhodium (Rh), hafnium (Hf), tantalum (Ta), tungsten (W), rhenium (Re), iridium (Ir), or platinum (Pt), may be provided.
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公开(公告)号:US20240138155A1
公开(公告)日:2024-04-25
申请号:US18547502
申请日:2022-03-20
Applicant: Peiching LIN
Inventor: Peiching LING , Nanray WU
IPC: H10B61/00 , H01L23/528 , H10B63/00
CPC classification number: H10B61/10 , H01L23/528 , H10B63/20
Abstract: A non-volatile memory device includes: an insulation layer; a Schottky diode, which is formed on the insulation layer; a writing wire which is conductive and is electrically connected to a first end of the Schottky diode: a memory unit on the Schottky diode, the memory unit being electrically connected to a second end of the Schottky diode: and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the Schottky diode to write the data into the memory unit.
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公开(公告)号:US11963368B2
公开(公告)日:2024-04-16
申请号:US17330295
申请日:2021-05-25
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Chun-Chieh Mo , Shih-Chi Kuo , Tsai-Hao Hung
CPC classification number: H10B63/24 , H10B61/10 , H10B63/80 , H10N50/01 , H10N50/10 , H10N50/80 , H10N70/021 , H10N70/063 , H10N70/231 , H10N70/24 , H10N70/245 , H10N70/826 , H10N70/841 , H10N50/85 , H10N70/8825 , H10N70/8833 , H10N70/8845
Abstract: A memory includes: a dielectric fin formed over a substrate; and a pair of memory cells disposed along respective sidewalls of the dielectric fin, each of the pair of memory cells comprising: a first conductor layer; a selector layer; a resistive material layer; and a second conductor layer, wherein the first conductor layer, selector layer, resistive material layer, and second conductor layer each includes upper and lower boundaries, and at least one of the upper and lower boundaries is tilted away from one of the sidewalls of the dielectric fin by an angle.
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公开(公告)号:US20240099156A1
公开(公告)日:2024-03-21
申请号:US18466868
申请日:2023-09-14
Applicant: Kioxia Corporation
Inventor: Kazuya SAWADA , Toshihiko NAGASE , Kenichi YOSHINO , Hyungjun CHO , Naoki AKIYAMA , Takuya SHIMANO , Tadaaki OIKAWA
Abstract: According to one embodiment, a magnetic memory device includes an electrode, and a magnetoresistance effect element provided on the electrode. The electrode includes a first electrode portion and a second electrode portion provided between the magnetoresistance effect element and the first electrode portion and containing a metal element selected from molybdenum (Mo) and ruthenium (Ru).
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公开(公告)号:US20240099153A1
公开(公告)日:2024-03-21
申请号:US18454960
申请日:2023-08-24
Applicant: Kioxia Corporation
Inventor: Takeshi IWASAKI , Zhu QI , Katsuyoshi KOMATSU , Jieqiong ZHANG
Abstract: A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a variable resistance layer disposed between the first conductive layer and the second conductive layer, and a switching layer disposed between the second conductive layer and the third conductive layer. The second conductive layer is disposed between the first conductive layer and the third conductive layer. The switching layer includes a first area, a second area, and a third area disposed between the first area and the second area. The first area includes a first element selected from Sn, Ga, Zn, Ta, Ti, and In, and O or N. The second area includes a second element selected from Sn, Ga, Zn, Ta, Ti, and In, and O or N. The third area includes a third element selected from Zr, Y, Ce, Hf, Al, Mg, and Nb, O or N, and a metal element selected from Te, Sb, Bi, Ti, and Zn.
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公开(公告)号:US11930717B2
公开(公告)日:2024-03-12
申请号:US17121523
申请日:2020-12-14
Inventor: Robert Beach , Guenole Jan , Yu-Jen Wang , Ru-Ying Tong
IPC: H10N50/80 , G11C11/16 , H01F10/12 , H01F10/32 , H01F41/30 , H01L29/82 , H10B61/00 , H10N50/10 , H10N50/85
CPC classification number: H10N50/80 , G11C11/161 , H01F10/123 , H01F10/3272 , H01F41/307 , H01L29/82 , H10B61/00 , H10B61/10 , H10N50/10 , H10N50/85 , H01F10/3286
Abstract: A synthetic antiferromagnetic structure for a spintronic device is disclosed and has an FL2/Co or Co alloy/antiferromagnetic coupling/Co or Co alloy/CoFeB configuration where FL2 is a ferromagnetic free layer with intrinsic PMA. Antiferromagnetic coupling is improved by inserting a Co or Co alloy dusting layer on top and bottom surfaces of the antiferromagnetic coupling layer. The FL2 layer may be a L10 ordered alloy, a rare earth-transition metal alloy, or an (A1/A2)n laminate where A1 is one of Co, CoFe, or an alloy thereof, and A2 is one of Pt, Pd, Rh, Ru, Ir, Mg, Mo, Os, Si, V, Ni, NiCo, and NiFe, or A1 is Fe and A2 is V. A method is also provided for forming the synthetic antiferromagnetic structure.
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公开(公告)号:US11875834B2
公开(公告)日:2024-01-16
申请号:US17465080
申请日:2021-09-02
Applicant: Kioxia Corporation
Inventor: Masayoshi Iwayama
CPC classification number: G11C11/161 , G06F13/4027 , G11C11/1655 , G11C11/1657 , G11C11/1659 , H10B61/10
Abstract: According to one embodiment, a magnetic memory device includes a first memory cell and a control circuit. The first memory cell includes a first magnetoresistance effect element and a first switching element coupled in series. The control circuit is configured to repeatedly apply a first voltage to the first memory cell until a first condition is satisfied in a first operation.
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公开(公告)号:US20230422518A1
公开(公告)日:2023-12-28
申请号:US18152122
申请日:2023-01-09
Inventor: Elia Ambrosi , Xinyu BAO , Cheng-Hsien Wu
Abstract: A memory device is provided. The memory device includes memory cells. Each of the memory cells includes: a resistance variable storage device; and a selector. The selector is stacked with the resistance variable storage device and coupled to the resistance variable storage device with a shared terminal, and includes a switching layer formed of a chalcogenide compound. A thickness of the switching layer is equal to or less than about 5 nm.
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公开(公告)号:US11856791B2
公开(公告)日:2023-12-26
申请号:US17750002
申请日:2022-05-20
Applicant: KIOXIA CORPORATION
Inventor: Masahiko Nakayama , Kazumasa Sunouchi , Gaku Sudo , Tadashi Kai
CPC classification number: H10B61/10 , H10N50/80 , G11C11/161 , H10N50/85
Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.
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