MEMORY DEVICE
    1.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号:US20240324242A1

    公开(公告)日:2024-09-26

    申请号:US18605999

    申请日:2024-03-15

    CPC classification number: H10B61/10 H10N50/10 H10N50/80

    Abstract: According to one embodiment, a memory device includes a first wiring line extending along a first direction, a second wiring line provided on an upper layer side of the first wiring line and extending along a second direction intersecting the first direction, and a memory cell provided between the first wiring line and the second wiring line, and including a magnetoresistance effect element, a switching element, a middle electrode provided between the magnetoresistance effect element and the switching element, and a resistive layer provided between the magnetoresistance effect element and the second wiring line. A resistance of the resistive layer is higher than a resistance of the middle electrode.

    NON-VOLATILE MEMORY DEVICE HAVING SCHOTTKY DIODE

    公开(公告)号:US20240138155A1

    公开(公告)日:2024-04-25

    申请号:US18547502

    申请日:2022-03-20

    Applicant: Peiching LIN

    CPC classification number: H10B61/10 H01L23/528 H10B63/20

    Abstract: A non-volatile memory device includes: an insulation layer; a Schottky diode, which is formed on the insulation layer; a writing wire which is conductive and is electrically connected to a first end of the Schottky diode: a memory unit on the Schottky diode, the memory unit being electrically connected to a second end of the Schottky diode: and a selection wire on the memory unit, the selection wire being electrically connected to the memory unit; wherein when the non-volatile memory device is selected for a data to be written into, a first current flows through the Schottky diode to write the data into the memory unit.

    STORAGE DEVICE
    6.
    发明公开
    STORAGE DEVICE 审中-公开

    公开(公告)号:US20240099153A1

    公开(公告)日:2024-03-21

    申请号:US18454960

    申请日:2023-08-24

    CPC classification number: H10N50/10 G11C5/08 H10B61/10 H10N50/85

    Abstract: A storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a variable resistance layer disposed between the first conductive layer and the second conductive layer, and a switching layer disposed between the second conductive layer and the third conductive layer. The second conductive layer is disposed between the first conductive layer and the third conductive layer. The switching layer includes a first area, a second area, and a third area disposed between the first area and the second area. The first area includes a first element selected from Sn, Ga, Zn, Ta, Ti, and In, and O or N. The second area includes a second element selected from Sn, Ga, Zn, Ta, Ti, and In, and O or N. The third area includes a third element selected from Zr, Y, Ce, Hf, Al, Mg, and Nb, O or N, and a metal element selected from Te, Sb, Bi, Ti, and Zn.

    MEMORY DEVICE
    9.
    发明公开
    MEMORY DEVICE 审中-公开

    公开(公告)号:US20230422518A1

    公开(公告)日:2023-12-28

    申请号:US18152122

    申请日:2023-01-09

    CPC classification number: H10B63/24 H10B61/10

    Abstract: A memory device is provided. The memory device includes memory cells. Each of the memory cells includes: a resistance variable storage device; and a selector. The selector is stacked with the resistance variable storage device and coupled to the resistance variable storage device with a shared terminal, and includes a switching layer formed of a chalcogenide compound. A thickness of the switching layer is equal to or less than about 5 nm.

    Nonvolatile storage device
    10.
    发明授权

    公开(公告)号:US11856791B2

    公开(公告)日:2023-12-26

    申请号:US17750002

    申请日:2022-05-20

    CPC classification number: H10B61/10 H10N50/80 G11C11/161 H10N50/85

    Abstract: A nonvolatile storage device includes first interconnections extending in a first direction and second interconnections extending in a second direction intersecting the first direction. Memory cells are formed at intersections between first and second interconnections. Each memory cell includes a resistance change element and a selector. In the arrangement of memory cells, all memory cells that are connected to any particular first interconnection are aligned along that first interconnection, and all memory cells connected to any particular second interconnection are alternately staggered in the first direction across a width of that second interconnection.

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