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公开(公告)号:US10217505B1
公开(公告)日:2019-02-26
申请号:US15692780
申请日:2017-08-31
Applicant: SanDisk Technologies LLC
Inventor: Mac D. Apodaca , Luiz Franca-Neto , Jordan Katine
Abstract: Apparatuses, systems, and methods are disclosed for a chip with phase change memory (PCM) and magnetoresistive random access memory (MRAM). An apparatus includes a semiconductor circuit formed over a substrate of a chip. An apparatus includes a PCM array formed over a semiconductor circuit. An apparatus includes an MRAM array formed over a semiconductor circuit.
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公开(公告)号:US12004357B2
公开(公告)日:2024-06-04
申请号:US17654768
申请日:2022-03-14
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Lei Wan , Jordan Katine , Tsai-Wei Wu , Chu-Chen Fu
Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.
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公开(公告)号:US10134457B1
公开(公告)日:2018-11-20
申请号:US15692920
申请日:2017-08-31
Applicant: SanDisk Technologies LLC
Inventor: Goran Mihajlovic , Jordan Katine , Neil Robertson , Neil Smith
Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A plurality of read lines are in a read line layer, and a plurality of write lines are in a write line layer. A plurality of spin accumulation lines are in a spin accumulation line layer disposed between a read line layer and a write line layer. Spin accumulation lines may horizontally cross read lines and write lines. A plurality of vertical magnetoresistive random access memory (MRAM) cells may include polarizers and magnetic tunnel junctions. A vertical MRAM cell may include a polarizer coupled between a spin accumulation line and a write line. A vertical MRAM cell may further include a magnetic tunnel junction coupled between a spin accumulation line and a read line, such that the magnetic tunnel junction and the polarizer are vertically aligned.
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公开(公告)号:US10056430B1
公开(公告)日:2018-08-21
申请号:US15793910
申请日:2017-10-25
Applicant: SanDisk Technologies LLC
Inventor: Goran Mihajlovic , Jordan Katine
CPC classification number: H01L27/222 , G11C11/005 , G11C11/161 , G11C11/1675 , H01L27/24 , H01L29/82 , H01L43/02 , H01L43/08 , H01L43/10
Abstract: Apparatuses, systems, and methods are disclosed for magnetoresistive random access memory. A magnetic tunnel junction for storing data may include a fixed layer, a barrier layer, and a composite free layer. A barrier layer may be disposed between a fixed layer and a composite free layer. A composite free layer may include one or more ferromagnetic layers. A composite free layer may include one or more anisotropy inducer layers that induce an in-plane magnetic anisotropy for the composite free layer in response to a perpendicular bias voltage.
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公开(公告)号:US12041787B2
公开(公告)日:2024-07-16
申请号:US17654760
申请日:2022-03-14
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Lei Wan , Jordan Katine
Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.
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公开(公告)号:US12004356B2
公开(公告)日:2024-06-04
申请号:US17654762
申请日:2022-03-14
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Lei Wan , Jordan Katine , Tsai-Wei Wu
Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.
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