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    Cross-point magnetoresistive random memory array and method of making thereof using self-aligned patterning
    1.
    发明授权
    Cross-point magnetoresistive random memory array and method of making thereof using self-aligned patterning 有权

    公开(公告)号：US12004357B2

    公开(公告)日：2024-06-04

    申请号：US17654768

    申请日：2022-03-14

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Lei Wan ,  Jordan Katine ,  Tsai-Wei Wu ,  Chu-Chen Fu

    IPC: G11C11/00 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

    CPC classification number: H10B61/10 ,  H10N50/01 ,  H10N50/80

    Abstract: A memory device includes a cross-point array of magnetoresistive memory cells. Each magnetoresistive memory cell includes a vertical stack of a selector-containing pillar structure and a magnetic tunnel junction pillar structure. The lateral spacing between neighboring pairs of magnetoresistive memory cells may be smaller along a first horizontal direction than along a second horizontal direction, and a dielectric spacer or a tapered etch process may be used to provide a pattern of an etch mask for patterning first electrically conductive lines underneath the magnetoresistive memory cells. Alternatively, a resist layer may be employed to pattern first electrically conductive lines underneath the cross-point array. Alternatively, a protective dielectric liner may be provided to protect selector-containing pillar structures during formation of the magnetic tunnel junction pillar structures.

    Resistive memory device including a lateral air gap around a memory element and method of making thereof
    2.
    发明授权
    Resistive memory device including a lateral air gap around a memory element and method of making thereof 有权

    公开(公告)号：US10050194B1

    公开(公告)日：2018-08-14

    申请号：US15478637

    申请日：2017-04-04

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Federico Nardi ,  Chu-Chen Fu

    IPC: H01L45/00 ,  H01L27/24

    Abstract: First electrically conductive lines can be formed over a substrate. A two-dimensional array of vertical stacks can be formed, each of which includes a first electrode, an in-process resistive memory material portion, and a second electrode over the first electrically conductive line. The sidewalls of the in-process resistive memory material portions are laterally recessed with respect to sidewalls of the first electrode and the second electrode to form resistive memory material portions having reduced lateral dimensions. A dielectric material layer is formed by an anisotropic deposition to form annular cavities that laterally surround a respective one of the resistive memory material portions. Second electrically conductive lines can be formed on the second electrodes.

    Implementation of VMCO area switching cell to VBL architecture
    3.
    发明授权
    Implementation of VMCO area switching cell to VBL architecture 有权

    公开(公告)号：US10026782B2

    公开(公告)日：2018-07-17

    申请号：US15633054

    申请日：2017-06-26

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Yoichiro Tanaka ,  Yangyin Chen ,  Chu-Chen Fu ,  Christopher Petti

    IPC: H01L47/00 ,  H01L27/24 ,  H01L45/00 ,  G11C13/00

    Abstract: Systems and methods for improving performance of a non-volatile memory that utilizes a Vacancy Modulated Conductive Oxide (VMCO) structure are described. The VMCO structure may include a layer of amorphous silicon (e.g., a Si barrier layer) and a layer titanium oxide (e.g., a TiO2 switching layer). In some cases, the VMCO structure or VMCO stack may use bulk switching or switching O-ion movements across an area of the VMCO structure, as opposed to switching locally in a constriction of vacancy formed filamentary path. A VMCO structure may be partially or fully embedded within a word line layer of a memory array.

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