公开(公告)号：US10283566B2

公开(公告)日：2019-05-07

申请号：US15610918

申请日：2017-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun Sel ,  Tuan Pham ,  Mitsuteru Mushiga ,  Yoshihiro Ikeda ,  Daewung Kang ,  Akio Nishida

IPC: H01L27/1157 ,  H01L27/11582 ,  H01L27/24 ,  H01L23/522 ,  H01L21/768 ,  H01L45/00

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.

公开(公告)号：US20180350879A1

公开(公告)日：2018-12-06

申请号：US15610918

申请日：2017-06-01

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jongsun Sel ,  Tuan Pham ,  Mitsuteru Mushiga ,  Yoshihiro Ikeda ,  Daewung Kang ,  Akio Nishida

IPC: H01L27/24 ,  H01L27/11582 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/768 ,  H01L45/00

CPC classification number: H01L27/2481 ,  H01L21/76879 ,  H01L23/5226 ,  H01L27/1157 ,  H01L27/11582 ,  H01L45/16

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, an array of memory structures, conductive structures located between a substrate and the alternating stack, conductive via structures, including an upper portion that overlies and contacts a top surface of a respective one of the electrically conductive layers, and a lower portion that underlies and is adjoined to the upper portion, contacts a top surface of a respective one of the conductive structures, and is electrically insulated from the rest of the electrically conductive layers. Inner, outer and intermediate dielectric spacers laterally surround a respective one of the conductive via structures.