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    Three-dimensional memory device containing a replacement buried source line and methods of making the same
    1.
    发明授权
    Three-dimensional memory device containing a replacement buried source line and methods of making the same 有权

    公开(公告)号：US10923496B2

    公开(公告)日：2021-02-16

    申请号：US16241171

    申请日：2019-01-07

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Mitsuteru Mushiga ,  Kenji Sugiura ,  Akio Nishida ,  Ryosuke Kaneko ,  Michiaki Sano

    IPC: H01L27/11582 ,  H01L21/8234 ,  H01L27/11565

    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures. The source-level semiconductor material layer may be electrically isolated from a substrate semiconductor material layer in the substrate by a series connection of two p-n junctions having opposite polarities.

    THREE-DIMENSIONAL DEVICE WITH BONDED STRUCTURES INCLUDING A SUPPORT DIE AND METHODS OF MAKING THE SAME
    2.
    发明申请
    THREE-DIMENSIONAL DEVICE WITH BONDED STRUCTURES INCLUDING A SUPPORT DIE AND METHODS OF MAKING THE SAME 审中-公开

    公开(公告)号：US20200295043A1

    公开(公告)日：2020-09-17

    申请号：US16891843

    申请日：2020-06-03

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Akio Nishida ,  Mitsuteru Mushiga

    IPC: H01L27/11582 ,  H01L23/00 ,  H01L23/528 ,  H01L27/1157 ,  H01L27/11573 ,  H01L23/522 ,  H01L25/18 ,  H01L21/28 ,  H01L21/768 ,  H01L27/11565

    Abstract: A memory die including a three-dimensional array of memory elements and a logic die including a peripheral circuitry that support operation of the three-dimensional array of memory elements can be bonded by die-to-die bonding to provide a bonded assembly. External bonding pads for the bonded assembly can be provided by forming recess regions through the memory die or through the logic die to physically expose metal interconnect structures within interconnect-level dielectric layers. The external bonding pads can include, or can be formed upon, a physically exposed subset of the metal interconnect structures. Alternatively or additionally, laterally-insulated external connection via structures can be formed through the bonded assembly to multiple levels of the metal interconnect structures. Further, through-dielectric external connection via structures extending through a stepped dielectric material portion of the memory die can be physically exposed, and external bonding pads can be formed thereupon.

    Three-dimensional memory device including a deformation-resistant edge seal structure and methods for making the same
    3.
    发明授权
    Three-dimensional memory device including a deformation-resistant edge seal structure and methods for making the same 有权

    公开(公告)号：US10665607B1

    公开(公告)日：2020-05-26

    申请号：US16251782

    申请日：2019-01-18

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Kenji Sugiura ,  Mitsuteru Mushiga ,  Yuji Fukano ,  Akio Nishida

    IPC: H01L27/11582 ,  H01L27/105 ,  H01L27/108 ,  H01L23/522 ,  H01L27/11568 ,  H01L21/768 ,  H01L27/11556

    Abstract: A vertically alternating stack of insulating layers and dielectric spacer material layers is formed over a semiconductor substrate. The vertically alternating stack is patterned into a first alternating stack located at a center region of a memory die and a second alternating stack that laterally encloses the first alternating stack. Memory stack structures are formed through the first alternating stack, and portions of the dielectric spacer material layers in the first alternating stack are replaced with electrically conductive layers while maintaining the second alternating stack intact. At least one metallic wall structure is formed through the second alternating stack. An edge seal assembly is provided, which includes at least one vertical stack of metallic seal structures. Each vertical stack of metallic seal structures vertically extends contiguously from a top surface of the semiconductor substrate to a bonding-side surface of the memory die, and includes a respective metallic wall structure.

    Methods and apparatus for three-dimensional nonvolatile memory
    4.
    发明授权
    Methods and apparatus for three-dimensional nonvolatile memory 有权

    公开(公告)号：US10115770B2

    公开(公告)日：2018-10-30

    申请号：US15445734

    申请日：2017-02-28

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Jongsun Sel ,  Daewung Kang ,  Michiaki Sano ,  Yohei Yamada ,  Mitsuteru Mushiga ,  Tuan Pham

    IPC: H01L21/00 ,  H01L27/115 ,  H01L21/8234 ,  H01L27/24 ,  H01L45/00 ,  H01L29/78 ,  H01L21/306

    Abstract: A method is provided that includes forming a dielectric material and a first sacrificial material above a substrate, forming a second sacrificial material above the substrate and disposed adjacent the dielectric material and the first sacrificial material, forming a first hole in the second sacrificial material, the first hole disposed in a first direction, forming a word line layer above the substrate via the first hole, the word line layer disposed in a second direction perpendicular to the first direction, forming a first portion of a nonvolatile memory material on peripheral sides of the word line layer via the first hole, forming a second hole in the second sacrificial material, forming a second portion of the nonvolatile memory material on a sidewall of the second hole, forming a local bit line in the second hole, and forming a memory cell including the nonvolatile memory material at an intersection of the local bit line and the word line layer.

    Three-dimensional memory device containing a replacement buried source line and methods of making the same
    6.
    发明授权
    Three-dimensional memory device containing a replacement buried source line and methods of making the same 有权

    公开(公告)号：US10797070B2

    公开(公告)日：2020-10-06

    申请号：US16241221

    申请日：2019-01-07

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Mitsuteru Mushiga ,  Kenji Sugiura ,  Akio Nishida

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L21/768 ,  H01L21/3213 ,  H01L27/1157 ,  H01L21/28

    Abstract: An alternating stack of insulating layers and spacer material layers is formed over a source-level sacrificial layer overlying a substrate. The spacer material layers are formed as, or are subsequently replaced with, electrically conductive layers. Memory stack structures including a respective vertical semiconductor channel and a respective memory film are formed through the alternating stack. A source-level cavity is formed by removing the source-level sacrificial layer. Semiconductor pillar structures may be used to provide mechanical support to the alternating stack during formation of the source-level cavity. A source-level semiconductor material layer can be formed in the source-level cavity. The source-level semiconductor material layer adjoins bottom end portions of the vertical semiconductor channels and laterally surrounds the semiconductor pillar structures. The source-level semiconductor material layer may be electrically isolated from a substrate semiconductor material layer in the substrate by a series connection of two p-n junctions having opposite polarities.

    Three-dimensional ReRAM memory device employing replacement word lines and methods of making the same
    9.
    发明授权
    Three-dimensional ReRAM memory device employing replacement word lines and methods of making the same 有权

    公开(公告)号：US10224373B2

    公开(公告)日：2019-03-05

    申请号：US15635321

    申请日：2017-06-28

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Jongsun Sel ,  Mitsuteru Mushiga ,  Vincent Shih ,  Akio Nishida ,  Tuan Pham

    IPC: H01L23/52 ,  H01L27/24 ,  H01L45/00 ,  H01L23/522 ,  H01L23/528

    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, resistive memory elements located in the alternating stack in first and second array regions and contact via structures located in a contact region between the first and the second array regions. The contact via structures have different depths and contact different electrically conductive layers. Support pillars are located in the contact region and extending through the alternating stack. At least one conduction channel area is located between the contact via structures in the contact region. The conduction channel area contains no support pillars, and all electrically conductive layers in the conduction channel area are continuous from the first array region to the second array region.

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