公开(公告)号：US20190013060A1

公开(公告)日：2019-01-10

申请号：US15941194

申请日：2018-03-30

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Deog-Kyoon JEONG ,  Jung Min YOON ,  Hyungrok DO

IPC: G11C11/4091 ,  H03F3/45 ,  G11C11/4099 ,  H03F1/02 ,  G11C11/4094

Abstract: An integrated circuit includes: an amplifier circuit including a first inverter and a second inverter to amplify a voltage difference between a first line and a second line; a replica amplifier circuit including a first replica inverter having an input terminal and an output terminal which are coupled to a second replica line and replicating the first inverter, and that includes a second replica inverter having an input terminal and an output terminal which are coupled to a first replica line and replicating the second inverter; and a current control circuit suitable for controlling an amount of a current sourced to the replica amplifier circuit and an amount of a current sunken from the replica amplifier circuit based on comparison of an average level between a voltage of the first replica line and a voltage of the second replica line with a level of a target voltage.

公开(公告)号：US20200075065A1

公开(公告)日：2020-03-05

申请号：US16545805

申请日：2019-08-20

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Deog-Kyoon JEONG ,  Jung Min YOON ,  Hyungrok DO ,  Dae-Hyun KOH

IPC: G11C7/06 ,  H03F1/02 ,  H03F3/16 ,  G11C11/22

Abstract: A BLSA circuit includes a first inverter disposed between a first sensing node and a second inner bit line, a second inverter disposed between a second sensing node and a first inner bit line, a first capacitor disposed between a first bit line and the first sensing node, a second capacitor disposed between a second bit line and the second sensing node, a first offset canceling switch for electrically coupling the first inner bit line with the second sensing node during an offset canceling operation, a second offset canceling switch for electrically coupling the second inner bit line with the first sensing node during the offset canceling operation, a first isolation switch for electrically coupling the first bit line with the first inner bit line, and a second isolation switch for electrically coupling the second bit line with the second inner bit line.

公开(公告)号：US20250117034A1

公开(公告)日：2025-04-10

申请号：US18437743

申请日：2024-02-09

Applicant: SK hynix Inc.

Inventor： Hyungrok DO ,  Dae Han KWON ,  Kyu Dong HWANG

IPC: G05F1/575 ,  G11C5/14

Abstract: An electronic device includes an internal voltage generation circuit configured to detect a voltage level of an internal voltage, that is generated by the internal voltage generation circuit. The internal voltage generating circuit is also configured to generate a drive code, which, along with a drive clock, determines the magnitude of the generated internal voltage. The drive code may be reset responsive to the internal voltage. The electronic device also includes a load circuit which is powered by the generated internal voltage.

公开(公告)号：US20200335937A1

公开(公告)日：2020-10-22

申请号：US16709669

申请日：2019-12-10

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Jeongho HWANG ,  Hong Seok CHOI ,  Hyungrok DO ,  Deog-Kyoon JEONG

IPC: H01S5/042 ,  H03K17/687

Abstract: A driving circuit includes an input circuit slice configured to convert a data signal into a first data signal and a second data signal having different DC components. The driving circuit also includes a driver slice configured to output driving current at an output node by generating push current or pull current according to the first data signal and the second data signal, wherein a magnitude of the push current or the pull current is variable.

公开(公告)号：US20200321977A1

公开(公告)日：2020-10-08

申请号：US16660653

申请日：2019-10-22

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Hong Seok CHOI ,  Jeongho HWANG ,  Hyungrok DO ,  Deog-Kyoon JEONG

IPC: H03M9/00 ,  H03K5/13 ,  H03K3/037 ,  H03K17/687

Abstract: A data serialization circuit includes a clock data operation circuit configured to generate a plurality of delay clock signals and a plurality of synchronous data signals in response to a plurality of parallel data signals and a plurality of multi-phase clock signals and a multiplexer configured to output a serial data signal in response to the plurality of delay clock signals and the plurality of synchronous data signals. A first one of the plurality of delay clock signals substantially aligns with a first one of the plurality of synchronous data signals.

公开(公告)号：US20200013459A1

公开(公告)日：2020-01-09

申请号：US16452325

申请日：2019-06-25

Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

Inventor： Hyungrok DO ,  Hong Seok CHOI ,  Deog-Kyoon JEONG

IPC: G11C13/00

Abstract: A semiconductor memory device includes a memory cell array including one or more memory cells each coupled between a wordline and a bitline, a sense amplifier configured to amplify a voltage of a global wordline, a wordline decoder including a plurality of wordline switches coupling the wordline and the global wordline, and a control circuit configured to control the wordline decoder and the sense amplifier.