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    RECEIVER, SYSTEM INCLUDING THE SAME, AND CALIBRATION METHOD THEREOF
    4.
    发明申请
    RECEIVER, SYSTEM INCLUDING THE SAME, AND CALIBRATION METHOD THEREOF 有权
    接收器，包括其的系统及其校准方法

    公开(公告)号：US20150139289A1

    公开(公告)日：2015-05-21

    申请号：US14498296

    申请日：2014-09-26

    Applicant: SK HYNIX INC. ,  Seoul National University R&DB Foundation

    Inventor： Han-Kyu CHI ,  Taek-Sang SONG ,  Seok-Min YE ,  Gi-Moon HONG ,  Woo-Rham BAE ,  Min-Seong CHU ,  Deog-Kyoon JEONG ,  Su-Hwan KIM

    IPC: H04L7/00 ,  H03K5/13 ,  H03K5/135 ,  H04L7/033

    CPC classification number: H04L7/0041 ,  H03K5/131 ,  H03K5/135 ,  H03K2005/0011 ,  H04L7/0008 ,  H04L7/0338 ,  H04L7/10 ,  H04L25/03057 ,  H04L25/14

    Abstract: A receiver includes a fixed delay unit configured to delay a first clock signal received from a clock channel by a predetermined time and output a second clock signal; a first delay unit configured to delay the first clock signal in response to a first control signal; a first data sampler configured to sample a data signal received from a data channel in response to an output signal of the first delay unit and output a first data signal; a second delay unit configured to delay the first data signal in response to a second control signal and output a second data signal; a second data sampler configured to sample the second data signal in response to the second clock signal; and a delay controller configured to output the first control signal and the second control signal.

    Abstract translation: 接收机包括固定延迟单元，其被配置为将从时钟信道接收的第一时钟信号延迟预定时间并输出第二时钟信号; 第一延迟单元，被配置为响应于第一控制信号延迟所述第一时钟信号; 第一数据采样器，被配置为响应于所述第一延迟单元的输出信号对从数据信道接收的数据信号进行采样，并输出第一数据信号; 第二延迟单元，被配置为响应于第二控制信号延迟所述第一数据信号并输出​​第二数据信号; 第二数据采样器，被配置为响应于所述第二时钟信号对所述第二数据信号进行采样; 以及延迟控制器，被配置为输出第一控制信号和第二控制信号。

    SEMICONDUCTOR DEVICE FOR ADJUSTING PHASES OF MULTI-PHASE SIGNALS
    5.
    发明申请
    SEMICONDUCTOR DEVICE FOR ADJUSTING PHASES OF MULTI-PHASE SIGNALS 有权

    公开(公告)号：US20210167783A1

    公开(公告)日：2021-06-03

    申请号：US17027570

    申请日：2020-09-21

    Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

    Inventor： Soyeong SHIN ,  Han-Gon KO ,  Deog-Kyoon JEONG

    IPC: H03L7/081 ,  G06F1/10 ,  H03K5/131

    Abstract: A semiconductor device includes a signal delay circuit configured to output a plurality of multi-phase output signals by delaying a plurality of multi-phase input signals according to a plurality of delay codes, respectively; and a calibration circuit including an error detection circuit configured to provide phase difference information between signals selected among the plurality of the multi-phase output signals according to a variable delay code and a filter configured to provide the plurality of delay codes and the variable delay code, wherein the filter performs update operation to update the plurality of delay codes or the variable delay code.

    INTEGRATED CIRCUIT AND MEMORY
    7.
    发明申请
    INTEGRATED CIRCUIT AND MEMORY 审中-公开

    公开(公告)号：US20200211605A1

    公开(公告)日：2020-07-02

    申请号：US16686941

    申请日：2019-11-18

    Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

    Inventor： Deog-Kyoon JEONG ,  Han-Gon KO ,  Chan-Ho KYE ,  So-Yeong SHIN

    IPC: G11C7/22 ,  G11C7/10 ,  H03L7/197 ,  H03L7/081

    Abstract: An integrated circuit includes: a first path suitable for transferring an input signal from a first point to a second point; a second path suitable for transferring the input signal from the second point to a third point; a first phase comparator suitable for comparing an edge of the input signal at the first point with an edge of the input signal at the second point; and a second phase comparator suitable for comparing an edge of the input signal at the second point with an edge of the input signal at the third point, wherein the first path includes a first delay circuit whose delay value is adjusted based on a comparison result of the first phase comparator, and the second path includes a second delay circuit whose delay value is adjusted based on a comparison result of the second phase comparator.

    SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF 有权
    半导体器件及其工作方法

    公开(公告)号：US20160149565A1

    公开(公告)日：2016-05-26

    申请号：US14839640

    申请日：2015-08-28

    Applicant: SK hynix Inc. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

    Inventor： Seok-Min YE ,  Suhwan KIM ,  Deog-Kyoon JEONG

    IPC: H03K5/1532 ,  H03K5/13

    CPC classification number: H03K5/1532 ,  H03K5/133

    Abstract: A semiconductor device may include: a variable delay circuit configured to delay a data strobe signal according to a delay control signal and output a delayed data strobe signal; a data sampler configured to compare a level of a reference voltage and a value of a data signal in synchronization with the delayed data strobe signal, and determine a logic level of the value of the data signal, the data signal having a training pattern; and a control circuit configured to determine a delay amount of the data strobe signal and generate the delay control signal and the reference voltage according to an output signal of the data sampler.

    Abstract translation: 半导体器件可以包括：可变延迟电路，被配置为根据延迟控制信号延迟数据选通信号并输出​​延迟的数据选通信号; 数据采样器，被配置为与所述延迟的数据选通信号同步地比较参考电压的电平和数据信号的值，并且确定所述数据信号的值的逻辑电平，所述数据信号具有训练模式; 以及控制电路，被配置为根据数据采样器的输出信号确定数据选通信号的延迟量并产生延迟控制信号和参考电压。

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