公开(公告)号：US09519020B2

公开(公告)日：2016-12-13

申请号：US13760242

申请日：2013-02-06

申请人： SK hynix Inc.

发明人： Jae Bum Ko ,  Jun Gi Choi

IPC分类号： G06F17/00 ,  G01R31/26 ,  G11C29/00 ,  G11C8/12 ,  G11C29/02 ,  H01L25/065

CPC分类号： G01R31/2607 ,  G06F17/00 ,  G11C8/12 ,  G11C29/027 ,  G11C29/785 ,  G11C29/848 ,  G11C29/883 ,  H01L25/0657 ,  H01L2225/06527 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor apparatus includes an individual chip designating code setting block configured to generate a plurality of individual chip designating code of different values; an individual chip activation block configured to enable an individual chip activation signal among a plurality of individual chip activation signals, which corresponds to individual chip designating code, when the individual chip designating code matches the individual chip control code; and a control block configured to set the individual chip control code or output chip selection address as the individual chip control code in response to chip selection fuse signals and test fuse signals.

摘要翻译： 一种半导体装置，包括单独的芯片指定代码设置块，其被配置为生成不同值的多个独立芯片指定代码; 单个芯片激活块，其被配置为当各个芯片指定代码与单独的芯片控制代码匹配时，使多个独立芯片激活信号中的各个芯片激活信号对应于各个芯片指定代码; 以及控制块，被配置为响应于芯片选择熔丝信号和测试熔丝信号，将单独的芯片控制代码或输出芯片选择地址设置为单独的芯片控制代码。

公开(公告)号：US09691456B2

公开(公告)日：2017-06-27

申请号：US14684502

申请日：2015-04-13

申请人： SK hynix Inc.

发明人： Bo Ra Choi ,  Ji Hyae Bae ,  Jun Gi Choi

IPC分类号： G11C11/00 ,  G11C8/18 ,  G11C8/10 ,  G11C8/12 ,  G11C7/20 ,  G11C29/44

CPC分类号： G11C8/18 ,  G11C7/20 ,  G11C8/10 ,  G11C8/12 ,  G11C2029/4402

摘要： A reconfigurable semiconductor memory apparatus may include a memory cell array including a plurality of sub arrays. The reconfigurable semiconductor memory apparatus may include an information storage unit configured to store status information for each sub array, and a reset address according to the status information.

公开(公告)号：US09607679B1

公开(公告)日：2017-03-28

申请号：US15169216

申请日：2016-05-31

申请人： SK hynix Inc.

发明人： Youk Hee Kim ,  Jun Gi Choi

IPC分类号： G11C7/00 ,  G11C11/406 ,  G11C11/409

CPC分类号： G11C11/40615 ,  G11C11/409 ,  G11C2211/4068

摘要： A refresh control device is disclosed, which relates to a technology for efficiently storing weak cell refresh addresses. The refresh control device includes a weak cell address storage circuit to store a weak address, a weak cell address control circuit, and a row address control circuit. The weak cell address control circuit outputs a weak enable signal and a row address by comparing a refresh address with the weak address, and only activates the refresh address according to the comparison result or activates both the refresh address and the row address. The row address control circuit controls a refresh operation by selectively activating a word line of a bank in response to the refresh address, the weak enable signal, and the row address.

公开(公告)号：US09583161B1

公开(公告)日：2017-02-28

申请号：US15246614

申请日：2016-08-25

申请人： SK hynix Inc.

发明人： Yong Seop Kim ,  Ji Hyae Bae ,  Min Chul Shin ,  Jun Gi Choi

IPC分类号： G11C17/18 ,  G11C7/22 ,  G11C8/08 ,  G11C8/10 ,  G11C29/00 ,  G11C17/16

CPC分类号： G11C29/781 ,  G11C8/14 ,  G11C17/16 ,  G11C17/18 ,  G11C29/785

摘要： A memory apparatus includes a first memory bank, a second memory bank, a row decoder and repair circuit, and an input/output driver controller. The row decoder and repair circuit is coupled to the first and second memory banks in common. The row decoder and repair circuit generates a shared repair signal according to whether a word line disposed in a first memory bank is replaced with a word line disposed in a second memory bank. The input/output driver controller allows read or write operations for one of the first and second memory banks to be performed based on the shared repair signal and an operation signal.

摘要翻译： 存储装置包括第一存储体，第二存储体，行解码器和修复电路以及输入/输出驱动器控制器。 行解码器和修复电路共同耦合到第一和第二存储体。 行解码器和修复电路根据设置在第一存储体中的字线是否被置于第二存储体中的字线代替共享修复信号。 输入/输出驱动器控制器允许基于共享修复信号和操作信号执行对第一和第二存储体之一的读或写操作。

公开(公告)号：US09019786B2

公开(公告)日：2015-04-28

申请号：US13720847

申请日：2012-12-19

申请人： SK Hynix Inc.

发明人： Jun Gi Choi ,  Choong Man Jung

IPC分类号： G11C29/00 ,  G11C29/44

CPC分类号： G11C29/787 ,  G11C29/006 ,  G11C29/802 ,  G11C2029/4402

摘要： A system for repairing a plurality of semiconductor chips each comprising a data storage region including electric fuses connected to the data storage regions of the plurality of semiconductor chips, a defect determination unit configured to read the data of a chip that is actually accessed and the data of an idle chip in the data storage regions, compare the actually accessed and read data with the data of the idle chip, and detect a defect based on a result of the comparison, a storage unit configured to store the defective position of the defect according to a result of the defect determination unit, and a repair unit configured to repair the defect through an E fuse connected to the position of the defect using a reset signal.

摘要翻译： 一种用于修复多个半导体芯片的系统，每个半导体芯片包括连接到多个半导体芯片的数据存储区域的电熔丝的数据存储区域，缺陷确定单元，被配置为读取实际访问的芯片的数据和数据 在数据存储区域中的空闲芯片，将实际访问和读取的数据与空闲芯片的数据进行比较，并且基于比较结果检测缺陷，存储单元，被配置为根据比较来存储缺陷的缺陷位置 以及修复单元，被配置为通过使用复位信号连接到缺陷的位置的E熔断器修复缺陷。