公开(公告)号：US20160146677A1

公开(公告)日：2016-05-26

申请号：US14695829

申请日：2015-04-24

申请人： SK hynix Inc.

发明人： Kyu Tae PARK ,  Marco PASSERINI

IPC分类号： G01K7/16

CPC分类号： G01K7/16

摘要： A temperature sensor includes a first current generating circuit configured to generate a first current being constant regardless of temperature changes, a cascode circuit configured to generate a cascode voltage, a second current generating circuit configured to generate a second current being in inverse proportion to temperature, and a compensated voltage output circuit configured to output a compensated voltage having various temperature coefficients in response to the first current and the second current.

摘要翻译： 温度传感器包括：第一电流产生电路，被配置为产生与温度变化无关的第一电流是恒定的;串联电路，被配置为产生共源共栅电压;第二电流产生电路，被配置为产生与温度成反比的第二电流; 以及补偿电压输出电路，被配置为响应于所述第一电流和所述第二电流输出具有各种温度系数的补偿电压。

公开(公告)号：US20220350762A1

公开(公告)日：2022-11-03

申请号：US17497472

申请日：2021-10-08

申请人： SK hynix Inc.

发明人： Kyu Tae PARK

IPC分类号： G06F13/24 ,  G06F13/16 ,  G06F13/40

摘要： A data communication apparatus includes a transceiver coupled to a data path and configured to transmit or receive data through the data path; and an interrupt circuit coupled to an interrupt path corresponding to the data path and configured to determine whether to allow any apparatus to occupy the data path. The interrupt circuit generates an interrupt signal for preventing another apparatus from accessing the data path, in response to an activation signal for transmitting or receiving the data through the transceiver.

公开(公告)号：US20220027091A1

公开(公告)日：2022-01-27

申请号：US17156128

申请日：2021-01-22

申请人： SK hynix Inc.

发明人： Kyu Tae PARK

IPC分类号： G06F3/06 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

摘要： Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including multiple planes, a peripheral circuit configured to perform an operation on the multiple planes, a control memory configured to store control codes for controlling the peripheral circuit, and a plurality of independent control logic configured to, when a command corresponding to each of the planes is received from a memory controller, control the peripheral circuit with reference to a control code corresponding to the command in response to the command. The control memory includes a common memory configured to be accessible in common by the plurality of independent control logic, and a temporary storage including areas respectively corresponding to the planes.

公开(公告)号：US20200342923A1

公开(公告)日：2020-10-29

申请号：US16722521

申请日：2019-12-20

申请人： SK hynix Inc.

发明人： Seong Ju LEE ,  Yun Tack HAN ,  Byung Deuk JEON ,  Kyu Tae PARK

IPC分类号： G11C7/22 ,  G11C7/10 ,  G01R31/317 ,  G11C29/44 ,  G11C8/18

摘要： A memory system includes a representative memory device directly outputting a representative data strobe signal, at least one non-representative memory device outputting a non-representative data strobe signal through the representative memory device, and a controller generating an internal delay clock signal synchronized with the representative data strobe signal. The controller outputs a test mode code defining a delay time using the internal delay clock signal as a reference signal. The at least one non-representative memory device adjusts a phase of the non-representative data strobe signal such that the non-representative data strobe signal has a delay time corresponding to the test mode code.

公开(公告)号：US20210096773A1

公开(公告)日：2021-04-01

申请号：US16864776

申请日：2020-05-01

申请人： SK hynix Inc.

发明人： Jin Yong SEONG ,  Kyu Tae PARK

IPC分类号： G06F3/06 ,  G11C16/04 ,  G11C16/30

摘要： Provided herein may be a storage device and a method of operating the storage device. A memory device may include a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform an operation on memory cells selected from among the plurality of memory cells, a voltage variation detector configured to generate voltage variation information indicating whether a voltage variation has occurred in a supply voltage during performance of the operation, a power register configured to store the voltage variation information, a status register configured to store status information indicating an operating status of the memory device, and a register output controller configured to update the status information provided from the status register based on the voltage variation information.