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    DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT
    2.
    发明申请
    DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT 有权

    公开(公告)号：US20210143807A1

    公开(公告)日：2021-05-13

    申请号：US17149479

    申请日：2021-01-14

    申请人： SK hynix Inc.

    发明人： Kyeong Min KIM ,  Yun Tack HAN

    IPC分类号： H03K5/14 ,  H03K5/131 ,  H03L7/099 ,  H03L7/089

    摘要： A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to nth output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n−1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding to delay cell, and a delay amount of the nth delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.

    DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT
    4.
    发明申请
    DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT 有权

    公开(公告)号：US20210152166A1

    公开(公告)日：2021-05-20

    申请号：US17157755

    申请日：2021-01-25

    申请人： SK hynix Inc.

    发明人： Kyeong Min KIM ,  Yun Tack HAN

    IPC分类号： H03K5/14 ,  H03K5/131 ,  H03L7/089 ,  H03L7/099

    摘要： A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to n-th output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n−1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding delay cell, and a delay amount of the n-th delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.

    MEMORY SYSTEMS HAVING A PLURALITY OF MEMORY DEVICES AND METHODS OF TRAINING THE MEMORY SYSTEMS
    5.
    发明申请
    MEMORY SYSTEMS HAVING A PLURALITY OF MEMORY DEVICES AND METHODS OF TRAINING THE MEMORY SYSTEMS 审中-公开

    公开(公告)号：US20200342923A1

    公开(公告)日：2020-10-29

    申请号：US16722521

    申请日：2019-12-20

    申请人： SK hynix Inc.

    发明人： Seong Ju LEE ,  Yun Tack HAN ,  Byung Deuk JEON ,  Kyu Tae PARK

    IPC分类号： G11C7/22 ,  G11C7/10 ,  G01R31/317 ,  G11C29/44 ,  G11C8/18

    摘要： A memory system includes a representative memory device directly outputting a representative data strobe signal, at least one non-representative memory device outputting a non-representative data strobe signal through the representative memory device, and a controller generating an internal delay clock signal synchronized with the representative data strobe signal. The controller outputs a test mode code defining a delay time using the internal delay clock signal as a reference signal. The at least one non-representative memory device adjusts a phase of the non-representative data strobe signal such that the non-representative data strobe signal has a delay time corresponding to the test mode code.

    DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT
    6.
    发明申请
    DELAY LINE, A DELAY LOCKED LOOP CIRCUIT AND A SEMICONDUCTOR APPARATUS USING THE DELAY LINE AND THE DELAY LOCKED LOOP CIRCUIT 有权

    公开(公告)号：US20230051365A1

    公开(公告)日：2023-02-16

    申请号：US17976586

    申请日：2022-10-28

    申请人： SK hynix Inc.

    发明人： Kyeong Min KIM ,  Yun Tack HAN

    IPC分类号： H03K5/14 ,  H03K5/131 ,  H03L7/089 ,  H03L7/099

    摘要： A delay line includes first to n-th delay cells and a dummy delay cell, ‘n’ being an integer greater than or equal to 3. The first to n-th delay cells sequentially delay an input signal to respectively generate first to n-th output signals. The dummy delay cell delays the n-th output signal based on a delay control voltage to generate a dummy output signal. A delay amount of each of the first to (n−1)-th delay cells is adjusted on a basis of the delay control voltage and the output signal of the delay cell of a next stage of the corresponding delay cell, and a delay amount of the n-th delay cell is adjusted on a basis of the delay control voltage and the dummy output signal.

    SEMICONDUCTOR APPARATUS INCLUDING A CLOCK PATH
    7.
    发明公开
    SEMICONDUCTOR APPARATUS INCLUDING A CLOCK PATH 审中-公开

    公开(公告)号：US20230350452A1

    公开(公告)日：2023-11-02

    申请号：US18350381

    申请日：2023-07-11

    申请人： SK hynix Inc.

    发明人： Yun Tack HAN ,  Sang Su LEE

    IPC分类号： H03K5/135 ,  H03L7/08 ,  G06F1/08

    CPC分类号： G06F1/08 ,  H03K5/135 ,  H03L7/0805

    摘要： A semiconductor apparatus includes an internal clock generating circuit, a stop controlling circuit, and a data clock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a clock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.

    SEMICONDUCTOR APPARATUS INCLUDING A CLOCK PATH
    8.
    发明申请
    SEMICONDUCTOR APPARATUS INCLUDING A CLOCK PATH 有权

    公开(公告)号：US20230082056A1

    公开(公告)日：2023-03-16

    申请号：US17557914

    申请日：2021-12-21

    申请人： SK hynix Inc.

    发明人： Yun Tack HAN ,  Sang Su LEE

    IPC分类号： G06F1/08 ,  H03L7/08 ,  H03K5/135

    摘要： A semiconductor apparatus includes an internal dock generating circuit, a stop controlling circuit, and a data dock generating circuit. The internal clock generating circuit generates, based on a reference clock signal, a plurality of internal clock signals. The stop controlling circuit generates a stop signal and a dock level signal based on the reference clock signal and the plurality of internal clock signals. The data clock generating circuit generates a data clock signal and a complementary data clock signal based on the plurality of internal clock signals, the stop signal, and the clock level signal.