公开(公告)号：US20210096773A1

公开(公告)日：2021-04-01

申请号：US16864776

申请日：2020-05-01

Applicant: SK hynix Inc.

Inventor： Jin Yong SEONG ,  Kyu Tae PARK

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/30

Abstract: Provided herein may be a storage device and a method of operating the storage device. A memory device may include a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform an operation on memory cells selected from among the plurality of memory cells, a voltage variation detector configured to generate voltage variation information indicating whether a voltage variation has occurred in a supply voltage during performance of the operation, a power register configured to store the voltage variation information, a status register configured to store status information indicating an operating status of the memory device, and a register output controller configured to update the status information provided from the status register based on the voltage variation information.

公开(公告)号：US20200174700A1

公开(公告)日：2020-06-04

申请号：US16515862

申请日：2019-07-18

Applicant: SK hynix Inc.

Inventor： Jin Yong SEONG

IPC: G06F3/06

Abstract: A memory device having an improved booting speed includes: a memory cell array, and a control logic configured to set a memory block as one of a special block for storing special information and a user block for storing user data and configured to store data in a memory block in response to commands from a memory controller, wherein the control logic comprises: a control signal generator configured to generate a special information read signal for reading plural pieces of special information stored in at least two special blocks among the plurality of memory blocks, in response to a special information read command provided by the memory controller, a special information merger configured to read the plural pieces of special information in response to the special information read signal, and a special information storage configured to store the read plural pieces of special information as merged special information.

公开(公告)号：US20190115052A1

公开(公告)日：2019-04-18

申请号：US15984803

申请日：2018-05-21

Applicant: SK hynix Inc.

Inventor： Jin Yong SEONG ,  Ho Jun KANG ,  Sang Bin PARK

IPC: G11C5/02 ,  G11C5/04 ,  G11C5/06 ,  G11C11/40 ,  G11C8/06 ,  G11C8/14 ,  H01L25/065 ,  H01L23/00

Abstract: Provided herein may be a memory chip, a package device having the memory chip, and a method of operating the package device. The memory chip comprising a plurality of memory blocks each including a plurality of memory cells for storing data; a plurality of input/output pads to which a chip address is inputted; and a plurality of peripheral circuits configured to program the chip address to a selected memory block among the memory blocks.

公开(公告)号：US20190391757A1

公开(公告)日：2019-12-26

申请号：US16256042

申请日：2019-01-24

Applicant: SK hynix Inc.

Inventor： Jin Yong SEONG ,  Jun Sang LEE

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/32

Abstract: In a storage device having an improved data receiving rate, the storage device includes: a plurality of memory devices each including a plurality of select signal pads; and a memory controller for providing a plurality of select signals representing a selected memory device among the plurality of memory devices through the plurality of select signal pads, wherein some select signals among the plurality of select signals include stack information indicating a number of the plurality of memory devices controlled by the memory controller.

公开(公告)号：US20150103606A1

公开(公告)日：2015-04-16

申请号：US14198151

申请日：2014-03-05

Applicant: SK hynix Inc.

Inventor： Jin Yong SEONG

IPC: G11C7/10

CPC classification number: G11C7/1066 ,  G11C7/1069 ,  G11C7/222

Abstract: A semiconductor device includes a data output circuit suitable for transferring an output data to an external data line during a data output operation, and a controller suitable for generating control signals for controlling the data output circuit during the data output operation, wherein the data output circuit senses a variation and transfers the output data to the external data line based on the sensing result.

Abstract translation: 半导体器件包括适于在数据输出操作期间将输出数据传送到外部数据线的数据输出电路，以及适于在数据输出操作期间产生用于控制数据输出电路的控制信号的控制器，其中数据输出电路 感测变化并基于感测结果将输出数据传送到外部数据线。

公开(公告)号：US20180174629A1

公开(公告)日：2018-06-21

申请号：US15638516

申请日：2017-06-30

Applicant: SK hynix Inc.

Inventor： Jin Yong SEONG ,  Gun Gi SONG ,  Young Sang AHN ,  Jae Won CHA

IPC: G11C7/24 ,  G11C7/10 ,  G06F11/30

CPC classification number: G11C7/24 ,  G06F11/3037 ,  G11C7/10 ,  G11C7/1063 ,  G11C16/22

Abstract: Provided herein may be a memory system and a method of operating the same. A semiconductor memory device may include a write protect pin mode setting unit configured to set, depending on a parameter value stored therein, a write protect pin of the semiconductor memory device as any one of an input pin and an output pin and a control logic configured to output, when the write protect pin serves as the output pin, internal state information of the semiconductor memory device to an external device.

公开(公告)号：US20180075910A1

公开(公告)日：2018-03-15

申请号：US15606798

申请日：2017-05-26

Applicant: SK hynix Inc.

Inventor： Jin Yong SEONG

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/24 ,  G11C11/34 ,  G11C11/063

CPC classification number: G11C16/10 ,  G06F13/16 ,  G11C7/1063 ,  G11C11/063 ,  G11C11/34 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/22 ,  G11C16/24 ,  G11C16/26 ,  G11C16/30 ,  G11C16/3436

Abstract: Provided herein are a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory cells, a status signal generator configured to output an internal status signal indicating whether an operation of the memory cell array has been completed or is being performed and a ready/busy line input mode control unit configured to output a ready/busy signal through a ready/busy line based on the internal status signal or to receive an input signal from an external device through the ready/busy line.

公开(公告)号：US20180108389A1

公开(公告)日：2018-04-19

申请号：US15632591

申请日：2017-06-26

Applicant: SK hynix Inc.

Inventor： Jin Yong SEONG

IPC: G11C7/10 ,  G11C16/34 ,  G11C11/56 ,  G11C16/04

CPC classification number: G11C7/1093 ,  G11C7/1051 ,  G11C7/1063 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/3404

Abstract: Provided herein are a semiconductor memory device and a method for operating the same. The semiconductor memory device includes a memory cell array, a status signal generator, an RB output control unit and a control logic. The memory cell array includes a plurality of memory cells. The status signal generator outputs an internal status signal indicating whether the memory cell array is performing an internal operation. The RB output control unit outputs a ready/busy signal based on the internal status signal. The control logic controls the RB output control unit to adjust an output current of the RB output control unit.

公开(公告)号：US20170276719A1

公开(公告)日：2017-09-28

申请号：US15225912

申请日：2016-08-02

Applicant: SK hynix Inc.

Inventor： Jin Yong SEONG

IPC: G01R31/26 ,  H01L21/78 ,  H01L23/544 ,  H01L21/66

CPC classification number: G01R31/2601 ,  H01L21/78 ,  H01L22/14 ,  H01L23/544 ,  H01L2223/5446

Abstract: A semiconductor apparatus may include a unit chip and a characteristic measurement circuit configured to include a plurality of unit elements for test and to output electrical characteristic information of the plurality of unit elements for test.

公开(公告)号：US20150109840A1

公开(公告)日：2015-04-23

申请号：US14166677

申请日：2014-01-28

Applicant: SK HYNIX INC.

Inventor： Jin Yong SEONG

IPC: G11C15/04

CPC classification number: G11C15/046 ,  G06F11/10 ,  G11C16/102 ,  G11C16/105 ,  G11C16/20

Abstract: A semiconductor device employs a technology for improving data retention characteristics of a cell array storing data regarding conditions for controlling internal operations of the semiconductor device. The semiconductor device includes a content addressable memory (CAM) cell array configured to store CAM data regarding conditions for controlling the internal operations, a control logic configured to store the CAM data read out of the CAM cell array, and a microprocessor configured to perform a reprogramming operation on the CAM cell array using the CAM data stored in the control logic.

Abstract translation: 半导体器件采用了用于提高存储关于控制半导体器件的内部操作的条件的数据的单元阵列的数据保持特性的技术。 半导体器件包括内容寻址存储器（CAM）单元阵列，其被配置为存储关于用于控制内部操作的条件的CAM数据，被配置为存储从CAM单元阵列读出的CAM数据的控制逻辑，以及被配置为执行 使用存储在控制逻辑中的CAM数据对CAM单元阵列进行重新编程操作。