公开(公告)号：US20220336499A1

公开(公告)日：2022-10-20

申请号：US17719052

申请日：2022-04-12

Applicant: Socionext Inc.

Inventor： Hideyuki KOMURO ,  Toshio HINO ,  Tomoya TSURUTA

IPC: H01L27/118

Abstract: In a power line structure for supplying power to standard cells, buried power lines extending in the X direction are placed at a given spacing in the Y direction. A local power line extending in the Y direction is connected with the buried power lines. Metal power lines extending in the X direction are formed in an upper-layer metal interconnect layer and connected with the local power line. The spacing of placement of the metal power lines in the Y direction is greater than the spacing of placement of the buried power lines.

公开(公告)号：US20240332304A1

公开(公告)日：2024-10-03

申请号：US18738947

申请日：2024-06-10

Applicant: Socionext Inc.

Inventor： Hideyuki KOMURO ,  Toshio HINO ,  Junji IWAHORI

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11881

Abstract: First and second semiconductor chips are stacked one upon the other with the back face of the first semiconductor chip opposed to the principal face of the second semiconductor chip. The first semiconductor chip includes: first and second power lines formed in a buried interconnect layer, extending in the X direction, and adjoining each other in the Y direction; first and second contacts provided between the first and second power lines and the chip back face; and a third contact provided between a signal line and the chip back face. The third contact is located between the first and second power lines in the Y direction, and at a position different from the positions of the first and second contacts in the X direction, in planar view.

公开(公告)号：US20240213300A1

公开(公告)日：2024-06-27

申请号：US18598870

申请日：2024-03-07

Applicant: Socionext Inc.

Inventor： Isaya SOBUE ,  Hideyuki KOMURO

IPC: H01L27/092 ,  H01L27/06 ,  H01L23/528

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L23/5286 ,  H01L27/092 ,  H01L27/0924

Abstract: A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.

公开(公告)号：US20250113594A1

公开(公告)日：2025-04-03

申请号：US18972119

申请日：2024-12-06

Applicant: Socionext Inc.

Inventor： Hideyuki KOMURO

IPC: H10D84/83 ,  H01L23/528 ,  H10D30/00

Abstract: A semiconductor integrated circuit device includes a plurality of standard cells each having a nanosheet field effect transistor (FET). A first standard cell includes a first buried power rail extending in the X direction and a nanosheet FET having a first nanosheet extending in the X direction. A second standard cell includes a second buried power rail greater in size in the Y direction than the first buried power rail and a nanosheet FET having a second nanosheet greater in size in the Y direction than the first nanosheet.

公开(公告)号：US20230411379A1

公开(公告)日：2023-12-21

申请号：US18458672

申请日：2023-08-30

Applicant: Socionext Inc.

Inventor： Hideyuki KOMURO

IPC: H01L27/02 ,  H01L27/092 ,  H01L23/522

CPC classification number: H01L27/0207 ,  H01L27/0924 ,  H01L27/0925 ,  H01L23/5221

Abstract: In a semiconductor integrated circuit device using buried power lines, a first standard cell includes a buried power line extending in the X direction to supply VDD1, and a transistor is supplied with VDD1 from the buried power line. A second standard cell includes a buried power line extending in the X direction to supply VDD1 and an upper-layer power line formed in a layer above the buried power line to supply VDD. A transistor of the second standard cell is supplied with VDD from the upper-layer power line. The upper-layer power line overlaps the buried power line in planar view.

公开(公告)号：US20240145390A1

公开(公告)日：2024-05-02

申请号：US18410874

申请日：2024-01-11

Applicant: SOCIONEXT INC.

Inventor： Hideyuki KOMURO ,  Junji IWAHORI

IPC: H01L23/528 ,  H01L23/535 ,  H01L27/092

CPC classification number: H01L23/5286 ,  H01L23/535 ,  H01L27/092

Abstract: A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.

公开(公告)号：US20210375863A1

公开(公告)日：2021-12-02

申请号：US17404639

申请日：2021-08-17

Applicant: SOCIONEXT INC.

Inventor： Hideyuki KOMURO ,  Tomoya TSURUTA ,  Yasuhiro NAKAOKA

IPC: H01L27/092 ,  H01L27/06 ,  H01L27/118 ,  H01L27/02 ,  H01L21/8238

Abstract: A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction.

公开(公告)号：US20210272904A1

公开(公告)日：2021-09-02

申请号：US17322570

申请日：2021-05-17

Applicant: SOCIONEXT INC.

Inventor： Hideyuki KOMURO ,  Junji IWAHORI

IPC: H01L23/528 ,  H01L27/092 ,  H01L23/535

Abstract: A layout structure of a capacitance cell using a complementary FET (CFET) is provided. A capacitance part includes a first three-dimensional transistor of a first conductivity type and a second three-dimensional transistor of a second conductivity type formed above the first transistor in the depth direction. The source and drain of the first transistor are both connected to VDD or VSS, and the source and drain of the second transistor are both connected to VDD or VSS. The gates of the first and second transistors are both connected to the gate of a transistor included in a fixed-value output part, and are supplied with VDD or VSS.

公开(公告)号：US20250006735A1

公开(公告)日：2025-01-02

申请号：US18882304

申请日：2024-09-11

Applicant: Socionext Inc.

Inventor： Hideyuki KOMURO ,  Tomoya TSURUTA ,  Yasuhiro NAKAOKA

IPC: H01L27/092 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/06 ,  H01L27/118

Abstract: A cell row includes an inverter cell having a logic function and a termination cell having no logic function. The termination cell is arranged at one of two ends of the cell row. A gate line and dummy gate lines are arranged in the same layer in a Z direction. Local interconnects are arranged in the same layer in the Z direction. Local interconnects are arranged in the same layer in the Z direction.

公开(公告)号：US20240363521A1

公开(公告)日：2024-10-31

申请号：US18763697

申请日：2024-07-03

Applicant: Socionext Inc.

Inventor： Hideyuki KOMURO

IPC: H01L23/50 ,  H01L27/02 ,  H01L27/088

CPC classification number: H01L23/50 ,  H01L27/0207 ,  H01L27/088

Abstract: In a semiconductor integrated circuit device using buried power lines, a standard cell includes: a first buried power line extending in the X direction and supplying a first power supply voltage; a second buried power line extending in the X direction and supplying a second power supply voltage; and a first transistor connected to the first power line. The first buried power line is spaced from the first transistor in planar view and located closer to the center of the standard cell than the first transistor in the Y direction.