公开(公告)号：US11557959B2

公开(公告)日：2023-01-17

申请号：US16959015

申请日：2018-12-29

申请人： CSMC TECHNOLOGIES FAB2 CO., LTD. ,  SOUTHEAST UNIVERSITY

发明人： Shen Xu ,  Minggang Chen ,  Hao Wang ,  Jinyu Xiao ,  Wei Su ,  Weifeng Sun ,  Longxing Shi

IPC分类号： H02M1/38 ,  H02M1/08 ,  H02M3/335 ,  H02M1/00

摘要： An automatic dead zone time optimization system in a primary-side regulation flyback power supply continuous conduction mode (CCM), including a closed loop formed by a control system, including a single output digital to analog converter (DAC) midpoint sampling module, a digital control module, a current detection module, a dead zone time calculation module and a pulse-width modulation (PWM) driving module, and a controlled synchronous rectification primary-side regulation flyback converter. A primary-side current is sampled using a DAC Sampling mechanism to calculate a secondary-side average current, so as to obtain a primary-side average current and a secondary-side average current, in the case of CCM. A secondary-side current is input into the dead zone time calculation module to obtain a reasonable dead zone time; and the PWM driving module is jointly controlled by a primary-side regulation loop and the obtained dead zone time.

公开(公告)号：US11770076B2

公开(公告)日：2023-09-26

申请号：US17420866

申请日：2020-06-19

申请人： SOUTHEAST UNIVERSITY ,  CSMC TECHNOLOGIES FAB2 CO., LTD.

发明人： Shen Xu ,  Minggang Chen ,  Wanqing Yang ,  Dejin Wang ,  Rui Jiang ,  Weifeng Sun ,  Longxing Shi

IPC分类号： H02M3/335 ,  H02M1/38 ,  H02M1/34

CPC分类号： H02M3/33569 ,  H02M1/342 ,  H02M1/38 ,  H02M3/33523

摘要： Disclosed are a system and method for controlling an active clamp flyback (ACF) converter. The system includes: a drive module configured to control turning-on or turning-off of a main switching transistor SL and a clamp switching transistor SH; a main switching transistor voltage sampling circuit configured to sample a voltage drop between an input terminal and an output terminal of the main switching transistor SL; a first comparator connected to the main switching transistor voltage sampling circuit and configured to determine whether a sampled first sampling voltage is a positive voltage or a negative voltage; and a dead time calculation module configured to adjust, according to an output of the first comparator and a main switching transistor control signal DUTYL of a current cycle, a clamp switching transistor control signal DUTYH of next cycle outputted by the drive module.