公开(公告)号：US11181940B2

公开(公告)日：2021-11-23

申请号：US16512696

申请日：2019-07-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jerome Chossat ,  Stephane Drouard

IPC: G06F1/08 ,  H03K19/21 ,  H03K5/156 ,  G06F11/277

Abstract: An electronic circuit includes a clock signal generator configured to deliver a clock signal. A propagation circuit is configured to propagate the clock signal on a plurality of propagation branches. A number of timers are coupled to at least some of the branches. The timers are clocked by corresponding replicas of the clock signal and configured to generate a pulse signal every N pulses of the corresponding replica of the clock signal. A comparator is configured to generate an alarm signal having a first state when two of the pulse signals are phase-offset with respect to one another.

公开(公告)号：US10063796B2

公开(公告)日：2018-08-28

申请号：US15088641

申请日：2016-04-01

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Tarek Lule ,  Benoit Deschamps ,  Jerome Chossat

IPC: H04N5/353 ,  H04N5/372 ,  H04N5/378

CPC classification number: H04N5/3535 ,  H04N5/35581 ,  H04N5/372 ,  H04N5/37452 ,  H04N5/378

Abstract: An electronic device disclosed herein includes a photodiode, and a plurality of storage components each configured to independently sample and hold charges from the photodiode during each of a plurality of integration periods without discharging the held charge between successive integration periods of the plurality thereof. Each storage component accumulates the charges from the photodiode for a given time window during each integration period, with the given time window for each storage component being different than the given time window for each other storage component. Readout circuitry is configured to transfer the charges from each storage component to a readout node in a respective read period for that storage component. The photodiodes and storage components are not configured to be reset between successive time windows during each integration period.

公开(公告)号：US20180084238A1

公开(公告)日：2018-03-22

申请号：US15467421

申请日：2017-03-23

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jerome Chossat ,  Olivier Le-Briz

IPC: H04N13/02

CPC classification number: H04N13/207 ,  H01L27/14607 ,  H01L27/14636 ,  H01L27/14645 ,  H01L27/14649 ,  H01L27/1469 ,  H04N5/3696 ,  H04N13/254 ,  H04N13/271

Abstract: A three dimensional (3D) device is formed from a first level and a second level that are attached together. The first level includes a backside illuminated two dimensional (2D) image sensor including an array of first pixels sensitive to visible light. The second level includes a frontside illuminated depth sensor including an array of second pixels sensitive to near infrared light. The first and second levels are attached in a manner such that radiation, in particular the near infrared light, received at the backside of the first level passes through the first level to reach the depth sensor in the second level.

公开(公告)号：US11889210B2

公开(公告)日：2024-01-30

申请号：US17575070

申请日：2022-01-13

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jerome Chossat ,  Mathieu Thivin

IPC: H04N25/68 ,  H04N25/772 ,  H04N25/702 ,  H04N25/76 ,  H04N25/683

CPC classification number: H04N25/68 ,  H04N25/772

Abstract: An electronic device includes a first array of image pixels having inputs coupled to first selection tracks and outputs coupled to first output tracks, a second array of test pixels having inputs coupled to second selection tracks and outputs coupled to the first output tracks, and a third array of test pixels having inputs coupled to the first selection tracks and outputs coupled to second output tracks. A processor is coupled to receive output signals on the first and second output tracks. The output signals from the test pixels of the second and third arrays are fixed at one or the other of only two values in the absence of a defect. The output signals received by the processor over the first and second output tracks are processed to determine presence or absence of a defect.

公开(公告)号：US11272118B2

公开(公告)日：2022-03-08

申请号：US16595192

申请日：2019-10-07

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Jerome Chossat ,  Benoit Deschamps ,  Adrien Martin

IPC: H04N5/235 ,  H04N5/225 ,  H04N5/3745 ,  H04N5/369 ,  H04N5/335 ,  G06T5/50

Abstract: An image device has an array of pixels, each pixel having a photosensitive area, a first storage node and a second storage node. A pixel is illuminated for a first period of time, and charge accumulated on the photosensitive area of the pixel during the first period of time is stored on the first storage node of the pixel. The pixel of the array is illuminated for a second period of time, and charge accumulated on the photosensitive area during the second period of time is stored on the second storage node of the pixel. A first signal is generated based on the charge stored on the first storage node, and a second signal is generated based on the charge stored on the second storage node. The first and second signals are combined using at least one subtraction operation having the first and second signals as operands.

公开(公告)号：US10455213B2

公开(公告)日：2019-10-22

申请号：US15467421

申请日：2017-03-23

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jerome Chossat ,  Olivier Le-Briz

IPC: H04N13/207 ,  H04N13/254 ,  H01L27/146 ,  H04N5/369 ,  H04N13/271

Abstract: A three dimensional (3D) device is formed from a first level and a second level that are attached together. The first level includes a backside illuminated two dimensional (2D) image sensor including an array of first pixels sensitive to visible light. The second level includes a frontside illuminated depth sensor including an array of second pixels sensitive to near infrared light. The first and second levels are attached in a manner such that radiation, in particular the near infrared light, received at the backside of the first level passes through the first level to reach the depth sensor in the second level.

公开(公告)号：US20200033907A1

公开(公告)日：2020-01-30

申请号：US16512696

申请日：2019-07-16

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jerome Chossat ,  Stephane Drouard

IPC: G06F1/08 ,  G06F11/277 ,  H03K5/156 ,  H03K19/21

Abstract: An electronic circuit includes a clock signal generator configured to deliver a clock signal. A propagation circuit is configured to propagate the clock signal on a plurality of propagation branches. A number of timers are coupled to at least some of the branches. The timers are clocked by corresponding replicas of the clock signal and configured to generate a pulse signal every N pulses of the corresponding replica of the clock signal. A comparator is configured to generate an alarm signal having a first state when two of the pulse signals are phase-offset with respect to one another.

公开(公告)号：US20170289473A1

公开(公告)日：2017-10-05

申请号：US15088641

申请日：2016-04-01

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Tarek Lule ,  Benoit Deschamps ,  Jerome Chossat

IPC: H04N5/353 ,  H04N5/378 ,  H04N5/372

CPC classification number: H04N5/3535 ,  H04N5/35581 ,  H04N5/372 ,  H04N5/37452 ,  H04N5/378

Abstract: An electronic device disclosed herein includes a photodiode, and a plurality of storage components each configured to independently sample and hold charges from the photodiode during each of a plurality of integration periods without discharging the held charge between successive integration periods of the plurality thereof. Each storage component accumulates the charges from the photodiode for a given time window during each integration period, with the given time window for each storage component being different than the given time window for each other storage component. Readout circuitry is configured to transfer the charges from each storage component to a readout node in a respective read period for that storage component. The photodiodes and storage components are not configured to be reset between successive time windows during each integration period.