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公开(公告)号:US10229484B2
公开(公告)日:2019-03-12
申请号:US15365086
申请日:2016-11-30
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Grégory Roffet , Mathieu Thivin
Abstract: Tone mapping is applied to pixels of a digital image. A luminance value of a pixel is determined based on whether one or more pixel intensity values of a pixel in a color space are within a pixel saturation range. A pixel gain is determined based on the determined luminance value of the pixel, and the determined pixel gain is applied to the pixel. The luminance value may also or instead be determined based on whether one or more of the pixel intensity values is within a pixel black-out range. A weight may be employed to determine the luminance value.
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公开(公告)号:US20180150946A1
公开(公告)日:2018-05-31
申请号:US15365086
申请日:2016-11-30
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Grégory Roffet , Mathieu Thivin
CPC classification number: G06T5/009 , G06T5/007 , G06T5/40 , G06T2207/10024 , G06T2207/20072 , G06T2207/20208 , H04N5/23229 , H04N5/243 , H04N9/045 , H04N9/68 , H04N9/77
Abstract: Tone mapping is applied to pixels of a digital image. A luminance value of a pixel is determined based on whether one or more pixel intensity values of a pixel in a color space are within a pixel saturation range. A pixel gain is determined based on the determined luminance value of the pixel, and the determined pixel gain is applied to the pixel. The luminance value may also or instead be determined based on whether one or more of the pixel intensity values is within a pixel black-out range. A weight may be employed to determine the luminance value.
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公开(公告)号:US09811920B2
公开(公告)日:2017-11-07
申请号:US15088923
申请日:2016-04-01
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Mathieu Thivin , Maurizio Colombo
Abstract: A digital image processing circuit processes macro-pixels of a digital image. A gain control parameter of each pixel of the macro-pixel of the digital image is determined based on a location of the pixel in the digital image. Relative pixel positions of the pixels of the macro-pixel are determined, the relative pixel positions representing pixel positions with respect to color grids. A gain value of each pixel of the macro-pixel is determined based on the relative pixel positions. The gain values are modified based on the gain control parameters. The modified gains are applied to the pixels of the macro-pixel.
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公开(公告)号:US10178359B2
公开(公告)日:2019-01-08
申请号:US15088934
申请日:2016-04-01
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Mathieu Thivin , Grégory Roffet
Abstract: Tone mapping is performed by digital image processing circuitry on a macro-pixel basis. A luminance value of a macro-pixel of a digital image in a color space is determined. The macro-pixel includes a plurality of individual pixels. Respective tone-mapping gain values of each pixel of the macro-pixel are determined based on the determined luminance value of the macro-pixel. The determined tone-mapping gains are applied to the respective pixels of the macro-pixel. The color space may be a CFA color space, such as a Bayer color space.
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公开(公告)号:US20170287141A1
公开(公告)日:2017-10-05
申请号:US15089077
申请日:2016-04-01
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Mathieu Thivin , Stephane Drouard
CPC classification number: G06T7/20 , G06T1/20 , G06T5/00 , G06T2200/28 , H04N1/00 , H04N1/6005 , H04N9/64
Abstract: Digital image processing circuitry converts images in a color filter array (CFA) color space to images in a luminance-chrominance (YUV) 4:2:0 color space, and the images in the YUV 4:2:0 color space are processed by the digital image processing circuitry in the YUV 4:2:0 color space, for example, to apply noise filtering, etc. The converting includes simultaneously receiving pixel data defining a macro-pixel in the CFA color space. The processing in the YUV color space is applied on a macro-pixel level to the macro-pixel of the image in the YUV color space.
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公开(公告)号:US10068342B2
公开(公告)日:2018-09-04
申请号:US15089077
申请日:2016-04-01
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Mathieu Thivin , Stephane Drouard
Abstract: Digital image processing circuitry converts images in a color filter array (CFA) color space to images in a luminance-chrominance (YUV) 4:2:0 color space, and the images in the YUV 4:2:0 color space are processed by the digital image processing circuitry in the YUV 4:2:0 color space, for example, to apply noise filtering, etc. The converting includes simultaneously receiving pixel data defining a macro-pixel in the CFA color space. The processing in the YUV color space is applied on a macro-pixel level to the macro-pixel of the image in the YUV color space.
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公开(公告)号:US09898831B2
公开(公告)日:2018-02-20
申请号:US15089134
申请日:2016-04-01
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Mathieu Thivin , Pierre-Francois Pugibet
CPC classification number: G06T7/90 , G06T3/4015 , G06T5/002 , G06T7/408 , G06T2207/10024 , H04N1/60
Abstract: Digital image processing circuitry converts a macro-pixel of an image in a color filter array (CFA) color space to a macro-pixel in a luminance-chrominance (YUV) color space. Chrominance filtering is applied to chrominance components of the converted macro-pixel in the YUV color space, generating a filtered macro-pixel in the YUV color space. The filtered macro-pixel in the YUV color space is converted into a filtered macro-pixel in the CFA color space.
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公开(公告)号:US20170287148A1
公开(公告)日:2017-10-05
申请号:US15088923
申请日:2016-04-01
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Mathieu Thivin , Maurizio Colombo
Abstract: A digital image processing circuit processes macro-pixels of a digital image. A gain control parameter of each pixel of the macro-pixel of the digital image is determined based on a location of the pixel in the digital image. Relative pixel positions of the pixels of the macro-pixel are determined, the relative pixel positions representing pixel positions with respect to color grids. A gain value of each pixel of the macro-pixel is determined based on the relative pixel positions. The gain values are modified based on the gain control parameters. The modified gains are applied to the pixels of the macro-pixel.
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公开(公告)号:US11889210B2
公开(公告)日:2024-01-30
申请号:US17575070
申请日:2022-01-13
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Jerome Chossat , Mathieu Thivin
IPC: H04N25/68 , H04N25/772 , H04N25/702 , H04N25/76 , H04N25/683
CPC classification number: H04N25/68 , H04N25/772
Abstract: An electronic device includes a first array of image pixels having inputs coupled to first selection tracks and outputs coupled to first output tracks, a second array of test pixels having inputs coupled to second selection tracks and outputs coupled to the first output tracks, and a third array of test pixels having inputs coupled to the first selection tracks and outputs coupled to second output tracks. A processor is coupled to receive output signals on the first and second output tracks. The output signals from the test pixels of the second and third arrays are fixed at one or the other of only two values in the absence of a defect. The output signals received by the processor over the first and second output tracks are processed to determine presence or absence of a defect.
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公开(公告)号:US10939094B2
公开(公告)日:2021-03-02
申请号:US16809926
申请日:2020-03-05
Inventor: Lookah Chua , Jansen Reyes Duey , Tarek Lule , Mathieu Thivin
IPC: H04N17/00 , H04N5/369 , H04N5/3745 , B60W30/09 , G08G1/16
Abstract: An electronic device includes a voltage divider producing different reference voltages. Dummy pixels each are formed by a transfer gate transistor having a first conduction terminal coupled to a floating diffusion node, a second conduction terminal, and a control node coupled to a first gate signal line, a transmission gate coupled between one of the plurality of taps and the second conduction terminal of the transfer gate transistor, a floating diffusion capacitor coupled between the floating diffusion node and ground, a transistor having a first conduction terminal coupled to the floating diffusion node, a second conduction terminal, and a control terminal coupled to a second gate signal line, and a reset transistor having a first conduction terminal coupled to the upper reference voltage, a second conduction terminal coupled to the second conduction terminal of the transistor, and a control terminal coupled to a reset signal line.
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