公开(公告)号：US11942935B2

公开(公告)日：2024-03-26

申请号：US17861067

申请日：2022-07-08

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Mark Wallis ,  Jean-Francois Link ,  Joran Pantel

IPC: H03K19/17724 ,  H03K19/173 ,  H03K19/17736 ,  H03K19/20

CPC classification number: H03K19/17724 ,  H03K19/1737 ,  H03K19/1774 ,  H03K19/17744 ,  H03K19/20

Abstract: An integrated circuit includes a programmable logic block. The programmable logic block includes a programmable logic array (PLA) and a field programmable gate array (FPGA). The PLA includes logic cells having a first architecture. The FPGA includes logic cells having a second architecture more complex than the first architecture. The programmable logic block includes an interface coupled to the PLA and the FPGA. An integrated circuit may also include circuitry for selecting one of plurality of clock signals for logic cells of a PLA.

公开(公告)号：US11855633B2

公开(公告)日：2023-12-26

申请号：US17827515

申请日：2022-05-27

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois Link ,  Mark Wallis ,  Joran Pantel

IPC: H03K19/17724 ,  H03K19/173 ,  H03K19/17704 ,  H03K3/0233 ,  H03K19/096

CPC classification number: H03K19/17724 ,  H03K3/0233 ,  H03K19/096 ,  H03K19/1737 ,  H03K19/17708

Abstract: An integrated circuit includes a programmable logic array. The programmable logic array incudes a plurality of logic elements arranged in rows and columns. Each logic element includes a direct output and a synchronized output. The direct output of each logic element is coupled to all other logic elements of higher rank, but is not coupled to logic elements of lower rank.

公开(公告)号：US20230126011A1

公开(公告)日：2023-04-27

申请号：US18045097

申请日：2022-10-07

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Olivier Ferrand ,  Jean-Francois Link

IPC: G06T1/60 ,  G06F12/10 ,  G06F12/0802

Abstract: In an embodiment a computer system includes at least one master module configured to process data having a format of N bits, a framebuffer configured to store pixel color component values of an image, the framebuffer having a resolution of N bits, each pixel being coded on P bits in the framebuffer and the pixels being stored one after another in the framebuffer and a memory management unit configured to control memory accesses of the at least one master module to the framebuffer, wherein the memory management unit is further configured to receive read memory access requests from the at least one master module, read at least one pixel in the framebuffer saved on P bits, and modify the format of the at least one read pixel by adding Q additional bits equal to a difference between N and P so as to format the at least one pixel on N bits before transmitting the at least one pixel to the at least one master module.

公开(公告)号：US10298109B2

公开(公告)日：2019-05-21

申请号：US15949690

申请日：2018-04-10

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jean-Francois Link ,  Vincent Onde

IPC: H02M1/08 ,  H03K4/08 ,  H03K3/017 ,  H03K7/08 ,  H02M1/00

Abstract: A control signal is applied to a pulse generating circuit configured to generate pulses that are modulated in width. A circuit provides for slope-compensation of the control signal. The circuit includes a digital-to-analog converter that generates a decreasing sawtooth signal. A triggering circuit operates to trigger steps of the sawtooth signal and resetting the sawtooth signal. The sawtooth signal is reset at a cadence of a frequency of the pulses that are modulated in width.

公开(公告)号：US10404263B2

公开(公告)日：2019-09-03

申请号：US15946324

申请日：2018-04-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Vincent Onde ,  Jean-Francois Link

IPC: H03M1/06 ,  H03K3/017 ,  H03K4/08

Abstract: A programmable digital-to-analog converter includes an analog circuit that converts a binary word into a value of analog voltage and a digital circuit that supplies the binary word starting from a maximum value decremented by a decrement value.

公开(公告)号：US11979153B2

公开(公告)日：2024-05-07

申请号：US17733934

申请日：2022-04-29

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Jean-Francois Link ,  Mark Wallis ,  Joran Pantel

IPC: H03K19/17736 ,  H03K19/173

CPC classification number: H03K19/17744 ,  H03K19/1737 ,  H03K19/1774

Abstract: A system on chip includes a programmable logic array. The system on chip also includes a signal conditioner coupled to a data input of the programmable logic array and configured to condition a data signal prior to processing the data signal with the programmable logic array. The signal conditioner can selectively condition the signal by one or both of synchronizing the data signal with a clock signal of the programmable logic array and generating a pulse from the data signal with an edge detector.