公开(公告)号：US09159425B2

公开(公告)日：2015-10-13

申请号：US14089016

申请日：2013-11-25

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics S.r.l.

Inventor： Vikas Rana ,  Ganesh Raj R ,  Fabio De Santis

IPC: G11C16/14 ,  G11C16/04

CPC classification number: G11C16/0433

Abstract: A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.

Abstract translation: 存储器包括非易失性存储器单元阵列。 每个单元包括与浮栅晶体管串联连接的选择晶体管。 单元可配置为在编程模式和擦除模式下操作。 当处于编程模式时，选择晶体管的栅极端子被负偏置电压驱动，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。 当处于擦除模式时，以负偏置电压驱动耦合到存储单元的下拉晶体管的栅极端子，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。

公开(公告)号：US20150146490A1

公开(公告)日：2015-05-28

申请号：US14089016

申请日：2013-11-25

Applicant: STMICROELECTRONICS INTERNATIONAL N.V. ,  STMICROELECTRONICS S.R.L.

Inventor： Vikas Rana ,  Ganesh Raj R ,  Fabio De Santis

IPC: G11C16/14

CPC classification number: G11C16/0433

Abstract: A memory includes an array of non-volatile memory cells. Each cell includes a select transistor in series connection with a floating gate transistor. The cells are configurable for operation in a programming mode and an erase mode. When in the programming mode, the gate terminal of the select transistor is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage. When in the erase mode, the gate terminal of a pull-down transistor coupled to the memory cell is driven with a negative bias voltage so as to bias that transistor in the accumulation region and eliminate sub-threshold leakage.

Abstract translation: 存储器包括非易失性存储器单元阵列。 每个单元包括与浮栅晶体管串联连接的选择晶体管。 单元可配置为在编程模式和擦除模式下操作。 当处于编程模式时，选择晶体管的栅极端子被负偏置电压驱动，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。 当处于擦除模式时，以负偏置电压驱动耦合到存储单元的下拉晶体管的栅极端子，以便在该累积区域中偏置该晶体管并消除次阈值泄漏。

公开(公告)号：US09325323B2

公开(公告)日：2016-04-26

申请号：US14474091

申请日：2014-08-30

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Vikas Rana ,  Ganesh Raj R

IPC: H03K3/03 ,  H03L1/00 ,  H03L7/14 ,  H03L7/18 ,  H03L7/093 ,  H03L7/089 ,  H03L7/081 ,  H03L7/099

CPC classification number: H03L1/00 ,  H03K3/011 ,  H03K3/0315 ,  H03K3/0322 ,  H03K3/354 ,  H03L1/022 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/0895 ,  H03L7/093 ,  H03L7/0995 ,  H03L7/0997 ,  H03L7/148 ,  H03L7/18

Abstract: A clock signal generation circuit configured to generate the clock signal having a frequency that is maintained across variations in a number of operating conditions, such as changes in supply voltage, temperature and processing time. In an embodiment, the frequency spread of the generated clock signal of a PVT-compensated CMOS ring oscillator is configured to compensate for variations in the supply voltage, as well as for variations in process and temperature via a process and temperature compensation circuit. The PVT-compensated CMOS ring oscillator includes a regulated voltage supply circuit to generate a supply voltage that is resistant to variations due to changes in the overall supply voltage.

Abstract translation: 时钟信号生成电路，被配置为生成具有在诸如电源电压，温度和处理时间的变化的操作条件的数量的变化中保持的频率的时钟信号。 在一个实施例中，PVT补偿的CMOS环形振荡器的所产生的时钟信号的频率扩展被配置为补偿电源电压的变化，以及通过处理和温度补偿电路对工艺和温度的变化。 PVT补偿的CMOS环形振荡器包括一个稳压电源，用于产生一个电源电压，该电源电压抵抗由于整个电源电压的变化引起的变化。