公开(公告)号：US20230055842A1

公开(公告)日：2023-02-23

申请号：US17882400

申请日：2022-08-05

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Salvatore Marco ROSSELLI ,  Giuseppe GUARNACCIA

IPC: G06F21/76 ,  G06F21/60

Abstract: A semiconductor device comprises one or more registers having digital signals stored therein. The semiconductor device is configured for communication with one or more external devices and such communication may involve requests for access to portions of these register or registers. Register shield circuitry is provided comprising access detection circuitry configured to detect requests for access to these register portions in communication with the external device or devices. The register shield circuitry is configured to be selectively activated in a register shield mode to shield these register portions from undesired requests for access. When activated in the register shield mode, the register shield circuitry prevents access to these register portions in response to requests for access detected by the access detection circuitry.

公开(公告)号：US20160099032A1

公开(公告)日：2016-04-07

申请号：US14508321

申请日：2014-10-07

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Salvatore Marco ROSSELLI ,  Giuseppe GUARNACCIA ,  Ugo MARI

IPC: G11C7/22

CPC classification number: G11C7/222 ,  G06F5/06 ,  G06F5/10 ,  G06F2205/102

Abstract: A bi-synchronous electronic device may include a FIFO memory circuit, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal, and write to the FIFO memory circuit based upon a write pointer. The bi-synchronous electronic device may include second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, and read from the FIFO memory circuit based upon a read pointer. The FIFO memory circuit may be configured to detect a jump in the write pointer to a new position, determine jump candidates for the read pointer from a current position, select a jump candidate, and synchronize the read pointer based upon the selected jump candidate.

Abstract translation: 双同步电子设备可以包括FIFO存储器电路和耦合到FIFO存储器电路并被配置为基于第一时钟信号进行操作的第一数字电路，并且基于写指针写入FIFO存储器电路。 双同步电子设备可以包括耦合到FIFO存储器电路并被配置为基于与第一时钟信号不同的第二时钟信号进行操作的第二数字电路，并且基于读指针从FIFO存储器电路读取。 FIFO存储器电路可以被配置为检测写指针中的跳转到新位置，从当前位置确定读指针的跳转候选，选择跳转候选，并且基于所选择的跳转候选来同步读指针。

公开(公告)号：US20160352337A1

公开(公告)日：2016-12-01

申请号：US14971150

申请日：2015-12-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Salvatore Marco ROSSELLI ,  Daniele MANGANO ,  Riccardo CONDORELLI

IPC: H03K19/177 ,  H03K19/00

CPC classification number: H03K19/0008 ,  G06F15/7867 ,  G06F2209/507 ,  H03K19/1737 ,  H03K19/1776

Abstract: A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.

Abstract translation: 电路包括组合电路和与其耦合的顺序电路元件。 电路包括耦合到组合和顺序电路元件的多路复用器，并且系统寄存器耦合到多路复用器。 组合和顺序电路元件的至少一部分被配置为选择性地切换为作为随机存取存储器操作。

公开(公告)号：US20160099031A1

公开(公告)日：2016-04-07

申请号：US14508126

申请日：2014-10-07

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Giuseppe GUARNACCIA ,  Salvatore Marco ROSSELLI

IPC: G11C7/22

CPC classification number: G06F5/10 ,  G06F2205/102 ,  G06F2205/106

Abstract: A bi-synchronous electronic device may include a FIFO memory circuit configured to store data, and a first digital circuit coupled to the FIFO memory circuit and configured to operate based upon a first clock signal and a write pointer, write a data burst to the FIFO memory circuit, thereby causing a jump in the write pointer to a new position, and write a burst indicator associated with the new position in the FIFO memory circuit. The bi-synchronous electronic device may include a second digital circuit coupled to the FIFO memory circuit and configured to operate based upon a second clock signal different from the first clock signal, read from the FIFO memory circuit based upon a read pointer, and synchronize the read pointer to the write pointer based upon the burst indicator.

Abstract translation: 双同步电子设备可以包括被配置为存储数据的FIFO存储器电路和耦合到FIFO存储器电路并被配置为基于第一时钟信号和写指针进行操作的第一数字电路，将数据脉冲串写入FIFO 从而导致写入指针跳到新位置，并且写入与FIFO存储器电路中的新位置相关联的突发指示符。 双同步电子设备可以包括耦合到FIFO存储器电路并被配置为基于与基于读取指针从FIFO存储器电路读取的与第一时钟信号不同的第二时钟信号进行操作的第二数字电路， 基于突发指示器读取指向写指针的指针。