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    POWER SUPPLY CIRCUIT, CORRESPONDING DEVICE AND METHOD
    1.
    发明申请
    POWER SUPPLY CIRCUIT, CORRESPONDING DEVICE AND METHOD 有权

    公开(公告)号：US20220397924A1

    公开(公告)日：2022-12-15

    申请号：US17836417

    申请日：2022-06-09

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele MANGANO ,  Francesco CLERICI ,  Pasquale BUTTA'

    IPC: G05F1/56 ,  G05F1/46

    Abstract: A voltage regulator coupled between a first node and second node includes a first (full-power) regulator circuit and a second (low-power) regulator circuit. In a first mode: the first regulator circuit is activated (with the second regulator circuit inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is kept de-activated when the voltage at the first node is a ground voltage. In a second mode: the first regulator circuitry in is active (with the second regulator circuitry inactive) when the voltage at the first node is a battery voltage, and the voltage regulator is inactive when the voltage at the first node is a ground voltage. In a third mode: the second regulator circuitry is active (with the first regulator circuitry inactive) irrespective of the voltage at the first node being at the battery voltage or the ground voltage.

    INTERFACE FOR A COMMUNICATION DEVICE AND RELATED METHODS
    3.
    发明申请
    INTERFACE FOR A COMMUNICATION DEVICE AND RELATED METHODS 有权
    一种通信设备的接口及相关方法

    公开(公告)号：US20160350258A1

    公开(公告)日：2016-12-01

    申请号：US14969642

    申请日：2015-12-15

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Daniele MANGANO ,  Riccardo Condorelli ,  Gaetano Distefano

    IPC: G06F13/42 ,  G06F13/40

    CPC classification number: G06F13/4282 ,  G06F13/4027 ,  G06F13/4291

    Abstract: A method that is for operating a serial protocol interface includes a communication device that is configured to exchange data over a communication link by sending output data on the communication link, and receiving input data on the communication link. The input data is synchronous with a clock signal generated at the communication device and propagated over the communication link. The method also includes initializing operation by sending the output data on the communication link at a first data rate, detecting a signal transition in the input data received on the communication link, and exchanging data over the communication link at a second data rate when the signal transition is detected, the second data rate being higher than the first data, with the exchanging of data at the second data rate synchronized as a function of the signal transition.

    Abstract translation: 一种用于操作串行协议接口的方法包括通信设备，其被配置为通过在通信链路上发送输出数据并在通信链路上接收输入数据来在通信链路上交换数据。 输入数据与在通信设备处生成的时钟信号同步并在通信链路上传播。 该方法还包括通过以第一数据速率发送通信链路上的输出数据来初始化操作，检测在通信链路上接收的输入数据中的信号转换，以及当信号以第二数据速率通过通信链路交换数据时 检测到转换，第二数据速率高于第一数据，以第二数据速率的数据交换作为信号转换的函数同步。

    METHOD OF OPERATING LC SENSORS, CORRESPONDING SYSTEM AND APPARATUS
    4.
    发明申请
    METHOD OF OPERATING LC SENSORS, CORRESPONDING SYSTEM AND APPARATUS 审中-公开

    公开(公告)号：US20190018051A1

    公开(公告)日：2019-01-17

    申请号：US16136121

    申请日：2018-09-19

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Riccardo CONDORELLI ,  Daniele MANGANO

    IPC: G01R27/26 ,  H03K17/95 ,  G01D5/20

    Abstract: In one embodiment, an inductive/LC sensor device includes: an energy storage device for accumulating excitation energy, an LC sensor configured to oscillate using energy accumulated in the energy storage device and transferred to the LC sensor, an energy detector for detecting the energy accumulated in the energy storage device reaching a charge threshold, and at least one switch coupled with the energy detector for terminating accumulating excitation energy in the energy storage device when the charge threshold is detected having been reached by the energy detector.

    METHOD AND SYSTEM FOR PERFORMING DIVISION/MULTIPLICATION OPERATIONS IN DIGITAL PROCESSORS, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT
    6.
    发明申请
    METHOD AND SYSTEM FOR PERFORMING DIVISION/MULTIPLICATION OPERATIONS IN DIGITAL PROCESSORS, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT 审中-公开

    公开(公告)号：US20190056910A1

    公开(公告)日：2019-02-21

    申请号：US16166977

    申请日：2018-10-22

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele MANGANO

    IPC: G06F5/01 ,  G06F7/535 ,  G06F7/52 ,  G06F7/523

    Abstract: A digital processor, such as, e.g., a divider in a PID controller, performs a mathematical operation such as division (or multiplication) involving operands represented by strings of bit signals and an operator to produce an operation result. The processor is configured by identifying first and second power-of-two approximating values of the operator as the nearest lower and nearest higher power-of-two values to the operator. The operation is performed on the input operands by means of the first and second power-of-two approximating values of the operator by shifting the bit signals in the operands by using the first and second power-of-two approximating values in an alternated sequence to produce: first approximate results by using the first power-of-two approximating value, second approximate results by using the second power-of-two approximating value. The average of the first and second approximate results is representative of the accurate result of the operation.

    RECONFIGURABLE SYSTEM-ON-CHIP AND RELATED METHODS
    7.
    发明申请
    RECONFIGURABLE SYSTEM-ON-CHIP AND RELATED METHODS 有权
    可重构的片上系统及相关方法

    公开(公告)号：US20160352337A1

    公开(公告)日：2016-12-01

    申请号：US14971150

    申请日：2015-12-16

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Salvatore Marco ROSSELLI ,  Daniele MANGANO ,  Riccardo CONDORELLI

    IPC: H03K19/177 ,  H03K19/00

    CPC classification number: H03K19/0008 ,  G06F15/7867 ,  G06F2209/507 ,  H03K19/1737 ,  H03K19/1776

    Abstract: A circuit includes combinational circuit and sequential circuit elements coupled thereto. The circuit includes a multiplexor coupled to the combinational and sequential circuit elements, and a system register is coupled to the multiplexor. At least one portion of the combinational and sequential circuit elements is configured to selectively switch to operate as a random access memory.

    Abstract translation: 电路包括组合电路和与其耦合的顺序电路元件。 电路包括耦合到组合和顺序电路元件的多路复用器，并且系统寄存器耦合到多路复用器。 组合和顺序电路元件的至少一部分被配置为选择性地切换为作为随机存取存储器操作。

    METHOD AND DEVICE FOR CLOCK CALIBRATION AND CORRESPONDING APPARATUS
    8.
    发明申请
    METHOD AND DEVICE FOR CLOCK CALIBRATION AND CORRESPONDING APPARATUS 审中-公开
    用于时钟校准和相关装置的方法和装置

    公开(公告)号：US20160246324A1

    公开(公告)日：2016-08-25

    申请号：US14965002

    申请日：2015-12-10

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Daniele MANGANO ,  Riccardo CONDORELLI

    IPC: G06F1/12 ,  G06F1/14

    CPC classification number: G06F1/12 ,  G06F1/14 ,  G06F1/3243 ,  H03L1/00 ,  Y02D10/152

    Abstract: A clock generator includes a microcontroller unit calibrated by aligning at subsequent calibration times a frequency of a first clock with respect to the frequency of a second clock having a higher frequency accuracy than the first clock, with the frequency of the first clock varying between subsequent calibration times. The frequency of the first clock is aligned to a frequency which is offset by a certain amount with respect to the frequency of the second clock to counter frequency error which may accumulate over time due to the variation in the frequency of the first clock.

    Abstract translation: 时钟发生器包括微处理器单元，该单元通过在随后的校准时间对准第一时钟的频率而相对于具有比第一时钟更高的频率精度的第二时钟的频率进行校准，第一时钟的频率在随后的校准之间变化 次 第一时钟的频率对应于相对于第二时钟的频率偏移一定量的频率，以对应于由于第一时钟的频率变化而随时间累积的对频率误差。

    SYSTEM AND METHOD FOR SELECTING AN OPERATING MODE, SUCH AS A BOOT MODE, OF A MICRO-CONTROLLER UNIT
    9.
    发明申请
    SYSTEM AND METHOD FOR SELECTING AN OPERATING MODE, SUCH AS A BOOT MODE, OF A MICRO-CONTROLLER UNIT 有权

    公开(公告)号：US20220263509A1

    公开(公告)日：2022-08-18

    申请号：US17671844

    申请日：2022-02-15

    Applicant: STMicroelectronics S.r.l.

    Inventor： Daniele MANGANO ,  Alessandro INGLESE

    IPC: H03K19/0175 ,  G06F13/12

    Abstract: A microcontroller includes an input pin and internal pull-up and pull-down circuits. External pull-up and pull-down circuits are also coupled to the input pin. The microcontroller is operable according to different configuration modes which include configuring the input pin in a floating state. A control logic then configures the internal pull-up and pull-down circuits according to an internal pull-up mode to acquire a first input voltage signal (at a first logic value) from the input pin, and further configure the internal pull-up and pull-down circuits according to an internal pull-down mode to acquire a second input voltage signal (at a second logic value) from the input pin. A selection of the operating mode of the MCU is then made based on the acquired first and second logic values.

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