Keys for elliptic curve cryptography

    公开(公告)号:US11831771B2

    公开(公告)日:2023-11-28

    申请号:US17506377

    申请日:2021-10-20

    CPC classification number: H04L9/3073 H04L9/0838 H04L9/3247 H04L2209/12

    Abstract: Cryptographic circuitry, in operation, generates N first pairs of elliptic curve cryptography (ECC) keys r(i), R(i), with i varying from 1 to N, using K second pairs of ECC keys p(k), P(k), with k varying from 1 to K, wherein K is smaller than N. Each pair r(i), R(i) of the first pairs of keys is a linear combination of pairs of the second pairs of ECC keys according to:






    i




    [

    1
    ;
    N

    ]



    {






    r

    (
    l
    )

    =




    j
    =
    1

    K



    A

    (

    i
    ,
    j

    )

    *

    p

    (
    j
    )










    R

    (
    i
    )

    =




    j
    =
    1

    K



    A

    (

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    ,
    j

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    P

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    ,







    wherein A(i,j) designates a general term of a matrix A of size N*K, and all the sub-matrices of size K*K are invertible. The cryptographic circuitry, in operation, executes cryptographic operations using one or more pairs of the first pairs of ECC keys.

    Monotonic counter
    2.
    发明授权

    公开(公告)号:US11715506B2

    公开(公告)日:2023-08-01

    申请号:US17691870

    申请日:2022-03-10

    CPC classification number: G11C8/04 G11C7/20

    Abstract: A monotonic counter stores N binary words representing a value in N memory cells. When i memory cells of consecutive ranks between k modulo N and k+i modulo N each represent a value complementary to a null value, the counter is incremented by erasing a value of a memory cell of rank k+i+1 modulo N. When i+1 memory cells of consecutive ranks between k+1 modulo N and k+i+1 modulo N each represent the value complementary to the null value, the counter is incremented by incrementing a value of a memory cell of rank k modulo N by two step sizes and storing a result in a memory cell of rank k+1 modulo N, wherein, N is an integer greater than or equal to five, k is an integer, and i is an integer between 2 and N−3.

    Read-once memory
    4.
    发明授权

    公开(公告)号:US11049567B2

    公开(公告)日:2021-06-29

    申请号:US16708316

    申请日:2019-12-09

    Inventor: Michael Peeters

    Abstract: A memory includes a rewritable non-volatile memory cell and input circuitry coupled to the memory cell. The input circuitry, in operation, erases the memory cell in response to reception of a request to read the memory cell. Similarly, a read-once memory includes an addressable, non-volatile memory having a plurality of rewriteable memory cells. Input circuitry coupled to the non-volatile memory responds to reception of a request to read content stored at an address in the non-volatile memory by erasing the content stored at the address of the non-volatile memory.

    MEMORY STORAGE DEVICE AND METHOD
    8.
    发明申请

    公开(公告)号:US20220327064A1

    公开(公告)日:2022-10-13

    申请号:US17653382

    申请日:2022-03-03

    Inventor: Michael Peeters

    Abstract: The present disclosure relates to secure storage, in a non-volatile memory, of initial data encrypted using a second data, including selecting a pointer aimed at an initial address of a memory cell of an initial part of the non-volatile memory, and encrypting the pointer using the second data; and-storing the encrypted pointer in the non-volatile memory.

    Monotonic counter
    10.
    发明授权

    公开(公告)号:US11776601B2

    公开(公告)日:2023-10-03

    申请号:US17691881

    申请日:2022-03-10

    CPC classification number: G11C8/04 G11C7/20

    Abstract: The present disclosure relates to a monotonic counter whose value is represented by a number N of binary words of N memory cells of a non-volatile memory, and being able to implement a step increment operation wherein if only one first memory cell represents a first value different from zero, then a second value equal to the said first value incremented by two times the said step is written into a second memory cell of rank directly higher than the rank of the first memory cell; and if a third and a fourth memory cell of consecutive ranks represent, respectively, a third value and a fourth value different from zero, then the third value of the third memory cell of lower rank is erased.

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