公开(公告)号：US09601381B2

公开(公告)日：2017-03-21

申请号：US14097565

申请日：2013-12-05

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Loubet ,  Stephane Monfray ,  Ronald Kevin Sampson

IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/84 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer. Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

公开(公告)号：US08877600B2

公开(公告)日：2014-11-04

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.A. ,  STMicroelectronics, Inc. ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/20 ,  H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US20140170834A1

公开(公告)日：2014-06-19

申请号：US14104903

申请日：2013-12-12

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat à l'Énergie Atomique et aux Énergies Alternatives ,  STMicroelectronics, Inc. ,  STMicroelectronics S.A.

Inventor： Claire Fenouillet-Beranger ,  Stephane Denorme ,  Nicolas Loubet ,  Qing Liu ,  Emmanuel Richard ,  Pierre Perreau

IPC: H01L21/762

CPC classification number: H01L21/76283 ,  H01L21/84 ,  H01L27/1207

Abstract: A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.

Abstract translation: 一种制造混合SOI /体基板的方法，包括以下步骤：在绝缘层上在单晶半导体衬底上从包括称为SOI层的单晶半导体层的SOI晶片开始; 在SOI层上沉积至少一个掩模层，并形成与掩模层，SOI层和绝缘层交叉的开口，以到达衬底; 通过选择性外延和部分蚀刻步骤的重复交替生长半导体材料; 以及蚀刻围绕填充有半导体材料的所述开口的绝缘沟槽，同时在开口的周边向内侵入。

公开(公告)号：US09601382B2

公开(公告)日：2017-03-21

申请号：US14940325

申请日：2015-11-13

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray ,  Ronald K. Sampson ,  Nicolas Loubet

IPC: H01L21/336 ,  H01L21/8234 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/84 ,  H01L29/10 ,  H01L29/165 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

公开(公告)号：US20160071772A1

公开(公告)日：2016-03-10

申请号：US14940325

申请日：2015-11-13

Applicant: STMicroelectronics, Inc. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Stephane Monfray ,  Ronald K. Sampson ,  Nicolas Loubet

IPC: H01L21/8234 ,  H01L29/165 ,  H01L29/10 ,  H01L29/78 ,  H01L21/84 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

公开(公告)号：US20150162433A1

公开(公告)日：2015-06-11

申请号：US14097565

申请日：2013-12-05

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS, INC.

Inventor： Nicolas Loubet ,  Stephane Monfray ,  Ronald Kevin Sampson

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/165 ,  H01L29/66

CPC classification number: H01L21/823431 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02573 ,  H01L21/823418 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L29/0673 ,  H01L29/1083 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

Abstract: Elongated fins of a first semiconductor material are insulated from and formed over an underlying substrate layer (of either SOI or bulk type). Elongated gates of a second semiconductor material are then formed to cross over the elongated fins at channel regions, and the gate side walls are covered by sidewall spacers. A protective material is provided to cover the underlying substrate layer and define sidewall spacers on side walls of the elongated fins between the elongated gates. The first semiconductor material and insulating material of the elongated fins located between the protective material sidewall spacers (but not under the elongated gates) is removed to form trenches aligned with the channel regions. Additional semiconductor material is then epitaxially grown inside each trench between the elongated gates to form source-drain regions adjacent the channel regions formed by the elongated fins of the first semiconductor material located under the elongated gates.

Abstract translation: 第一半导体材料的细长散热片与下层基底层（SOI或本体型）绝缘和形成。 然后形成第二半导体材料的细长的栅极，以在沟道区域上跨过细长的翅片，并且栅极侧壁被侧壁间隔物覆盖。 提供保护材料以覆盖下面的基底层并且在细长门之间限定细长翅片的侧壁上的侧壁间隔物。 位于保护材料侧壁间隔件（但不在细长门下）的细长翅片的第一半导体材料和绝缘材料被去除以形成与沟道区域对准的沟槽。 然后在细长门之间的每个沟槽内外延生长另外的半导体材料，以形成邻近由位于细长栅极下方的第一半导体材料的细长鳍片形成的沟道区域的源极 - 漏极区域。

公开(公告)号：US11264286B2

公开(公告)日：2022-03-01

申请号：US16445778

申请日：2019-06-19

Applicant: STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Pierre Morin ,  Yann Mignot

IPC: H01L29/78 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/165 ,  H01L21/02 ,  H01L21/762 ,  H01L29/49 ,  H01L29/06 ,  H01L29/417

Abstract: Integrated circuits are disclosed in which the strain properties of adjacent pFETs and nFETs are independently adjustable. The pFETs include compressive-strained SiGe on a silicon substrate, while the nFETs include tensile-strained silicon on a strain-relaxed SiGe substrate. Adjacent n-type and p-type FinFETs are separated by electrically insulating regions formed by a damascene process. During formation of the insulating regions, the SiGe substrate supporting the n-type devices is permitted to relax elastically, thereby limiting defect formation in the crystal lattice of the SiGe substrate.

公开(公告)号：US20190189802A1

公开(公告)日：2019-06-20

申请号：US16212632

申请日：2018-12-06

Applicant: STMICROELECTRONICS, INC.

Inventor： Pierre Morin ,  Nicolas Loubet

IPC: H01L29/78 ,  H01L29/165 ,  H01L29/66 ,  H01L27/088

CPC classification number: H01L29/7848 ,  H01L27/0886 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, and source and drain regions adjacent the channel region to generate shear and normal strain on the channel region. A semiconductor device may include a substrate, a fin above the substrate and having a channel region therein, source and drain regions adjacent the channel region, and a gate over the channel region. The fin may be canted with respect to the source and drain regions to generate shear and normal strain on the channel region.

公开(公告)号：US10283418B2

公开(公告)日：2019-05-07

申请号：US16027889

申请日：2018-07-05

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMicroelectronics, Inc.

Inventor： Hong He ,  James Kuss ,  Nicolas Loubet ,  Junli Wang

IPC: H01L21/84 ,  H01L21/8238 ,  H01L21/02 ,  H01L21/306 ,  H01L21/324 ,  H01L27/092 ,  H01L27/12 ,  H01L29/161

Abstract: A method for forming fin field effect transistors for complementary metal oxide semiconductor (CMOS) devices includes filling, with a dielectric fill, areas between fin structures formed on a substrate, the fin structures including a silicon layer formed on a SiGe layer; removing the SiGe layer of a first region of the fin structures by selectively etching the fin structures from the end portions of the fin structures to form voids; exposing the silicon layer of the fin structures in the first region and a second regions; and thermally oxidizing the SiGe layer in the second region, forming SiGe fins on a second dielectric material in the second region and silicon fins on the first dielectric material in the first region.

公开(公告)号：US10204982B2

公开(公告)日：2019-02-12

申请号：US14048232

申请日：2013-10-08

Applicant: STMicroelectronics, Inc.

Inventor： Pierre Morin ,  Qing Liu ,  Nicolas Loubet

IPC: H01L29/06 ,  H01L21/84 ,  H01L27/12 ,  H01L29/78 ,  H01L21/8238

Abstract: A method for forming a semiconductor device includes forming a mask layer on a stressed semiconductor layer of a stressed, semiconductor-on-insulator wafer. An isolation trench bounding the stressed semiconductor layer is formed. The isolation trench extends through the mask layer and into the SOI wafer past an oxide layer thereof. A dielectric body is formed in the isolation trench. A relaxation reduction liner is formed on the dielectric body and on an adjacent sidewall of the stressed semiconductor layer. The mask layer on the stressed semiconductor layer is removed.