公开(公告)号：US10578672B2

公开(公告)日：2020-03-03

申请号：US14986053

申请日：2015-12-31

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Jacquet ,  Didier Fuin

IPC: G01R31/317 ,  G01R31/3177 ,  G01R31/3185

Abstract: A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.

公开(公告)号：US10386414B2

公开(公告)日：2019-08-20

申请号：US15324851

申请日：2015-05-28

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Jean-Marc Daveau ,  Philippe Roche ,  Didier Fuin

IPC: G01R31/3185 ,  G01R31/3177 ,  G01R31/317

Abstract: A device may include a control circuit configured to place, after a normal mode operation of N flip-flops, the N flip-flops in a test mode in which the test input of the first flip-flop of the chain is intended to receive a first sequence of test bits A memory may be configured to store a sequence of N values delivered by the test output of the last flip-flop of the chain. The control circuit may be configured to deliver, at the test input of the first flip-flop of the chain, the sequence of N stored values to restore the state of the N flip-flops before their placement in the test mode.

公开(公告)号：US10346322B2

公开(公告)日：2019-07-09

申请号：US15355188

申请日：2016-11-18

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Arthur Stoutchinin ,  Didier Fuin ,  Mario Toma

IPC: G06F13/00 ,  G06F13/16 ,  G06F15/82 ,  G06F11/36 ,  G06F9/448 ,  G06F8/34

Abstract: An electronic system implements a software application described in the form of a graph of the Kahn network type, and includes actors. At least one of the actors includes a processor, and at least another one of the actors includes a hardware accelerator. Buffer memories are coupled between the actors. A central processor is configured to enable communications between the actors according to a communications and synchronization protocol. The processor and the hardware accelerator are configured to use different individual communications protocols.

公开(公告)号：US20170192053A1

公开(公告)日：2017-07-06

申请号：US14986053

申请日：2015-12-31

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： David Jacquet ,  Didier Fuin

IPC: G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/3177 ,  G01R31/31703 ,  G01R31/31708 ,  G01R31/318566 ,  G01R31/318569

Abstract: A digital circuit includes a scan chain which loads data into and unloads data from the digital circuit. Checking circuitry is coupled to the scan chain and generates a first digital signature based on data indicative of a pre-testing status of the digital circuit as the data is unloaded from the digital circuit via the scan chain. When testing is completed, the data is restored to the digital circuit via the scan chain. The checking circuitry generates a second digital signature as the data is loaded into the digital circuit. The first digital signature is compared to the second digital signature to verify an integrity of the process. A specific data pattern may be loaded into the scan chain as the data is unloaded. An output of the scan chain may be monitored to detect the pattern and an error signal may be generated based on when the pattern is detected.