公开(公告)号：US20210232174A1

公开(公告)日：2021-07-29

申请号：US17159511

申请日：2021-01-27

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Shenzhen) R&D Co. Ltd

Inventor： Ignazio PISELLO ,  Yu Yong WANG ,  Dario ARENA ,  Qi Yu LIU

IPC: G06F1/06 ,  G01R31/317

Abstract: A combinational circuit block has input pins configured to receive input digital signals and output pins configured to provide output digital signals as a function of the input digital signals received. A test input pin receives a test input signal. A test output pin provides a test output signal as a function of the test input signal received. A set of scan registers are selectively coupled to either the combinational circuit block or to one another so as to form a scan chain of scan registers serially coupled between the test input pin and the test output pin. The scan registers in the set of scan registers are clocked by a clock signal. At least one input register is coupled between the test input pin and a first scan register of the scan chain. The at least one input register is clocked by an inverted replica of the clock signal.

公开(公告)号：US20190123694A1

公开(公告)日：2019-04-25

申请号：US16222281

申请日：2018-12-17

Applicant: STMicroelectronics (Shenzhen) R&D Co. Ltd

Inventor： Ru Feng DU ,  Qi Yu LIU

IPC: H03F1/32 ,  H03G3/34 ,  H03F1/30 ,  H03F3/45 ,  H04R3/00 ,  H03F3/183 ,  H03F3/217 ,  H03F1/02 ,  H03F3/185 ,  H03F3/187 ,  H03F3/21

CPC classification number: H03F1/3205 ,  H03F1/0205 ,  H03F1/305 ,  H03F3/183 ,  H03F3/185 ,  H03F3/187 ,  H03F3/211 ,  H03F3/2171 ,  H03F3/2173 ,  H03F3/45179 ,  H03F2200/03 ,  H03F2200/351 ,  H03F2203/21106 ,  H03F2203/45151 ,  H03F2203/45156 ,  H03G3/345 ,  H03G3/348 ,  H04R3/002

Abstract: A class D amplifier receives and amplifies a differential analog signal which is then differentially integrated. Two pulse width modulators generate pulse signals corresponding to the differentially integrated analog signal and two power units generate output pulse signals. The outputs the power units are coupled to input terminals of integrators via a resistor feedback network. An analog output unit converts the pulse signals to an output analog signal. The differential integration circuitry implements a soft transition between mute/un-mute. In mute, the integrator output is fixed. During the soft transition, the PWM outputs change slowly from a fixed 50% duty cycle to a final value to ensure that no pop noise is present in the output as a result of mode change.