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公开(公告)号：US20240056046A1
公开(公告)日：2024-02-15
申请号：US18493282
申请日：2023-10-24
发明人： XiangSheng Li , Ru Feng Du
CPC分类号： H03G3/3005 , H03F3/187 , H04R3/00 , H04R29/00 , H03F2200/03 , H03G2201/103
摘要： An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.
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公开(公告)号：US11831286B2
公开(公告)日：2023-11-28
申请号：US17241980
申请日：2021-04-27
发明人： XiangSheng Li , Ru Feng Du
CPC分类号： H03G3/3005 , H03F3/187 , H04R3/00 , H04R29/00 , H03F2200/03 , H03G2201/103
摘要： An audio amplifier includes: a buck controller configured to control an output voltage at a first supply terminal, the output voltage selected from a set including a plurality of output voltages, where the output voltage takes a settling time to settle; a first audio bridge including: a class-AB driver stage coupled to the first supply terminal, and a delay insertion circuit configured to receive a processed digital stream and provide the processed digital stream to the class-AB driver stage a delay time after receiving the processed digital stream, where the delay time is based on the settling time; and an audio amplitude detector configured to detect a first peak amplitude in the first digital audio stream, where the buck controller is configured to select a lowest output voltage from the set that is higher than the first peak amplitude plus a headroom voltage.
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3.发明公开公开(公告)号：US20230216458A1
公开(公告)日：2023-07-06
申请号：US17568732
申请日：2022-01-05
发明人： Che-Wei Hsu , Wun-Long Yu
CPC分类号： H03F3/217 , H03F3/187 , H03F3/45475 , H03F2200/03
摘要： A driving circuit of a loudspeaker includes a periodic signal generation circuit, a signal processing circuit, a class-D amplifier circuit, a current sensing circuit, and a sample and hold circuit. The periodic signal generation circuit is arranged to generate a periodic signal and a control signal. The signal processing circuit is coupled to the periodic signal generation circuit, and is arranged to generate a pre-driving signal. The class-D amplifier circuit is coupled to the signal processing circuit, and is arranged to drive the loudspeaker according to the pre-driving signal. The current sensing circuit is coupled to the class-D amplifier circuit, and is arranged to generate a current sensing signal. The sample and hold circuit is coupled to the periodic signal generation circuit and the current sensing circuit, and is arranged to sample and hold the current sensing signal according to the control signal, to generate a current sampling signal.
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公开(公告)号：US20190036497A1
公开(公告)日：2019-01-31
申请号：US15917895
申请日：2018-03-12
发明人： JongPal KIM
IPC分类号： H03F3/04 , A61B5/024 , A61B5/0428
CPC分类号： H03F3/04 , A61B5/02416 , A61B5/0428 , A61B5/04284 , A61B5/04288 , A61B5/7225 , H03F1/26 , H03F3/187 , H03F3/45475 , H03F2200/231 , H03F2200/249 , H03F2200/252 , H03F2200/261 , H03F2200/372 , H03F2200/462 , H03F2200/471 , H03F2200/75 , H03F2203/45022 , H03F2203/45258
摘要： Disclosed is a reconfigurable amplifier and an amplification method thereof, the amplifier includes an input selector, a first amplifying circuit, and a second amplifying circuit. The input selector is configured to select one of a voltage input and a current input based on a voltage measurement mode and a current measurement mode. The first amplifying circuit includes a first load element, and is configured to apply a voltage corresponding to the voltage input to the first load element in the voltage measurement mode and receive the current input in the current measurement mode and block a current flowing through the first load element. The second amplifying circuit is configured to mirror a current flowing through the first amplifying circuit in response to one of the voltage input and the current input and generate an output voltage based on the mirrored current.
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公开(公告)号：US10116473B1
公开(公告)日：2018-10-30
申请号：US15926395
申请日：2018-03-20
CPC分类号： H04L25/4927 , H03F1/0227 , H03F1/025 , H03F3/187 , H03F3/213 , H03F2200/03 , H03F2200/331 , H04B14/046 , H04L25/03159 , H04R3/04
摘要： An apparatus may include a delta-sigma modulator for quantization noise shaping of a digital signal, a digital-to-analog converter configured to generate an analog signal from the digital signal, and an amplifier configured to amplify the analog signal and powered from a charge pump, wherein the charge pump is configured to operate at a switching frequency approximately equal to a zero of a modulator noise transfer function of the delta-sigma modulator, such that the impact of charge pump noise on a total harmonic distortion noise of the apparatus is minimized.
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公开(公告)号：US20180276172A1
公开(公告)日：2018-09-27
申请号：US15743540
申请日：2015-07-10
发明人： Guohua CHEN , Zhiqiang CHEN
CPC分类号： G06F13/42 , G05B19/042 , H01J21/10 , H03F1/26 , H03F3/181 , H03F3/187 , H03F3/45 , H03F3/45475 , H03F2200/03
摘要： The utility model discloses a circuit for inhibiting single-ended analogue signal noises and a terminal accessory. The circuit includes an input interface module, a differential amplification module, an analogue signal processing module, an isolation module and a control module, wherein the input interface module at least includes an analogue signal line and a digital signal line, the differential amplification module includes differential input ends and an output end; the analogue signal line and the digital signal line of the input interface module are respectively connected to the differential input ends of the differential amplification module, so that the analogue signal line and the digital signal line form a pseudo-differential pair, and the output end of the differential amplification module is connected to the analogue signal processing module; the digital signal line is further connected to the isolation module, and the isolation module is further connected to the control module.
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公开(公告)号：US20180241363A1
公开(公告)日：2018-08-23
申请号：US15691867
申请日：2017-08-31
发明人： Takafumi Kiyono
IPC分类号： H03F3/217
CPC分类号： H03F3/2173 , H03F3/185 , H03F3/187 , H03F3/45475 , H03F2200/03 , H03F2200/66
摘要： A class-D amplifier of an embodiment includes: a PWM modulator configured to output a PWM pulse based on an input signal; a first output transistor group, in which a connection point of complementarily operated two first output transistors is an output end; a second output transistor group, in which a connection point of complementarily operated two second output transistors is connected to the connection point of the first transistors; a driver circuit capable of driving the first output transistors and the second output transistors of the first and second output transistor groups, based on the PWM pulse from the PWM modulator; and a control circuit configured to generate a control signal for operating at least one of the first output transistor group and the second output transistor group.
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公开(公告)号：US10056915B2
公开(公告)日：2018-08-21
申请号：US14937175
申请日：2015-11-10
发明人： Akinobu Onishi
IPC分类号： H04B15/00 , H03M1/66 , H03M1/00 , H03M3/00 , H03M1/70 , H03M1/06 , H04R3/00 , H03F3/45 , H03F3/187
CPC分类号： H03M1/661 , H03F3/187 , H03F3/45475 , H03F2200/03 , H03F2203/45526 , H03M1/002 , H03M1/0626 , H03M1/70 , H03M3/32 , H03M3/344 , H03M3/502 , H03M3/508 , H03M3/51 , H04R3/00
摘要： A digital-to-analog converter (DAC) circuit includes a first DAC that produces a first analog output signal based upon a received multi-bit digital signal and upon a received clock. A second DAC that produces a second analog output signal based upon the received multi-bit digital signal and upon the received clock, wherein the first and second DACs are connected in parallel and process the same multi-bit digital signal. In one embodiment, the DACs produce differential signals. A low pass filter connected to receive the first and second analog outputs is configured to sum the first and second analog outputs and to filter the summed first and second analog outputs to produce an ingoing analog signal. An amplifier is connected to receive the ingoing analog signal to produce an amplified ingoing analog signal.
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公开(公告)号：US10003312B2
公开(公告)日：2018-06-19
申请号：US14841490
申请日：2015-08-31
CPC分类号： H03F3/183 , H03F1/34 , H03F1/56 , H03F3/187 , H03F3/45071 , H03F3/45475 , H03F2200/03 , H03F2200/234 , H03F2200/387 , H03F2203/45136 , H03F2203/45521 , H03F2203/45522 , H03F2203/45528 , H04R3/00 , H04R2420/03 , H04R2420/05
摘要： An apparatus includes a resistor having an input coupled to an output of an amplifier. The apparatus also includes a feedback circuit coupled to an output of the resistor and to an input of the amplifier. The feedback circuit includes a first component of a voltage divider.
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公开(公告)号：US20180159490A1
公开(公告)日：2018-06-07
申请号：US15886103
申请日：2018-02-01
发明人： John Paul LESSO , Toru IDO
CPC分类号： H03G3/3089 , H03F1/26 , H03F1/32 , H03F1/34 , H03F3/187 , H03F3/217 , H03F3/2171 , H03F3/2173 , H03F3/2175 , H03F2200/102 , H03F2200/339 , H03F2200/432 , H03G7/002 , H03G7/007
摘要： This application relates to Class D amplifier circuits (200). A modulator (201) controls a Class D output stage (202) based on a modulator input signal (Dm) to generate an output signal (Vout) which is representative of an input signal (Din). An error block (205), which may comprise an ADC (207), generates an error signal (ϵ) from the output signal and the input signal. In various embodiments the extent to which the error signal (ϵ) contributes to the modulator input signal (Dm) is variable based on an indication of the amplitude of the input signal (Din). The error signal may be received at a first input (204) of a signal selector block (203). The input signal may be received at a second input (206) of the signal selector block (203). The signal selector block may be operable in first and second modes of operation, wherein in the first mode the modulator input signal is based at least in part on the error signal; and in the second mode the modulator input signal is based on the digital input signal and is independent of the error signal. The error signal can be used to reduce distortion at high signal levels but is not used at low signal levels and so the noise floor at low signal levels does not depend on the component of the error block (205).
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