公开(公告)号：US09436610B2

公开(公告)日：2016-09-06

申请号：US14464750

申请日：2014-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Gilles Ries ,  Ennio Salemi ,  Sana Ben Alaya

IPC: G06F12/00 ,  G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/1027 ,  G06F12/1063 ,  G06F2212/304 ,  G06F2212/507 ,  G06F2212/602 ,  G06F2212/684

Abstract: A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.

Abstract translation: 存储器管理单元可以将页面表移动请求发送到主存储器系统中的页表描述符并且接收地址转换信息，其中页表步行请求包括指定进一步的地址转换信息的量的信息，并且接收另外的地址转换 信息。 高速缓存单元可以拦截页表行走请求，并且修改被拦截的页表行走请求的内容，使得指定进一步的地址转换信息量的信息从第一数量扩展到大于第一数量的第二数量。 高速缓存单元可以存储第二数量的进一步的地址转换信息，以便与当前数据请求之后的数据请求一起使用，并且基于与已经存储在地址转换信息中的地址转换信息相关联的被拦截的页表移动请求来提供地址转换信息 缓存单元。

公开(公告)号：US20150058578A1

公开(公告)日：2015-02-26

申请号：US14464750

申请日：2014-08-21

Applicant: STMicroelectronics International N.V.

Inventor： Gilles Ries ,  Ennio Salemi ,  Sana Ben Alaya

IPC: G06F12/08 ,  G06F12/10

CPC classification number: G06F12/0862 ,  G06F12/1027 ,  G06F12/1063 ,  G06F2212/304 ,  G06F2212/507 ,  G06F2212/602 ,  G06F2212/684

Abstract: A memory management unit may send page table walk requests to a page table descriptor in a main memory system and receive address translation information, with the page table walk requests including information that specifies an amount of further address translation information, and receive the further address translation information. The cache unit may intercept the page table walk requests, and modify content of the intercepted page table walk requests so the information that specifies the amount of further address translation information is extended from a first amount to a second amount greater than the first amount. The cache unit may store the second amount of further address translation information for use with data requests that are subsequent to a current data request, and provide the address translation information based upon an intercepted page table walk request being associated with address translation information already stored in the cache unit.

Abstract translation: 存储器管理单元可以将页面表移动请求发送到主存储器系统中的页表描述符并且接收地址转换信息，其中页表步行请求包括指定进一步的地址转换信息的量的信息，并且接收另外的地址转换 信息。 高速缓存单元可以拦截页表行走请求，并且修改被拦截的页表行走请求的内容，使得指定进一步的地址转换信息量的信息从第一数量扩展到大于第一数量的第二数量。 高速缓存单元可以存储第二数量的进一步的地址转换信息，以便与当前数据请求之后的数据请求一起使用，并且基于与已经存储在地址转换信息中的地址转换信息相关联的被拦截的页表移动请求来提供地址转换信息 缓存单元。

公开(公告)号：US09946652B2

公开(公告)日：2018-04-17

申请号：US14486215

申请日：2014-09-15

Applicant: STMicroelectronics International N.V.

Inventor： Gilles Ries ,  Ennio Salemi ,  Sana Ben Alaya

IPC: G06F12/00 ,  G06F12/0862 ,  G06F12/1027

CPC classification number: G06F12/0862 ,  G06F12/1027 ,  G06F2212/602 ,  G06F2212/654

Abstract: A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit. The control circuitry may be configured to generate a blank data request including a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request.

公开(公告)号：US20150081983A1

公开(公告)日：2015-03-19

申请号：US14486215

申请日：2014-09-15

Applicant: STMicroelectronics International N.V.

Inventor： Gilles Ries ,  Ennio Salemi ,  Sana Ben Alaya

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F12/1027 ,  G06F2212/602 ,  G06F2212/654

Abstract: A memory management system for managing a memory and includes a multi-stage memory management unit including control circuitry and cache memory. The cache memory may have a respective translation look-aside buffer for each stage of the multi-stage memory management unit. The control circuitry may be configured to generate a blank data request including a virtual address and information that specifies that data is not to be read from the memory, perform address translations based on the generated blank data request in multiple stages until a physical address is obtained, and discard the blank data request.

Abstract translation: 一种用于管理存储器并且包括包括控制电路和高速缓冲存储器的多级存储器管理单元的存储器管理系统。 高速缓存存储器可以具有用于多级存储器管理单元的每个级的相应的翻译后备缓冲器。 控制电路可以被配置为生成包括虚拟地址的空白数据请求和指定不从存储器读取数据的信息，基于生成的空白数据请求，以多级执行地址转换，直到获得物理地址 ，并丢弃空白数据请求。