公开(公告)号：US20250069656A1

公开(公告)日：2025-02-27

申请号：US18813662

申请日：2024-08-23

Applicant: STMicroelectronics International N.V.

Inventor： Maurizio Francesco Perroni ,  Fabio Enrico Carlo Disegni ,  Cesare Torti ,  Davide Manfré ,  Massimo Caruso

IPC: G11C13/00

Abstract: A memory device comprises a memory array having memory cells in a set of memory portions and addressable via a pair of row and column values, a set of sense amplifier circuits coupled to and interposed between adjacent memory portions, a control logic circuit configured to provide at least one address signal indicating a pair of row and column values to localize at least one addressed memory cell, and to issue read or write access requests towards the at least one addressed memory cell, a first set of access devices configured to couple an addressed memory cell in a respective memory portion to a respective sense amplifier circuit in response to a read access request, and a second set of access devices configured to couple an addressed memory cell in a respective memory portion to a main programming bitline in response to a write access request.

公开(公告)号：US20250030418A1

公开(公告)日：2025-01-23

申请号：US18764672

申请日：2024-07-05

Applicant: STMicroelectronics International N.V.

Inventor： Maurizio Francesco Perroni ,  Davide Manfré ,  Massimo Caruso ,  Cesare Torti ,  Fabio Enrico Carlo Disegni

IPC: H03K17/687

Abstract: A switch circuit includes a first and a second input nodes to receive a first and a second input voltages, and an output node to produce an output voltage switchable between the first and second input voltages. A first and a second pass devices are arranged in series between the first input node and the output node. A third and a fourth pass devices are arranged in series between the second input node and the output node. A first, a second, a third, and a fourth elevator circuits control, respectively, the first, second, third, and fourth pass devices. The first elevator circuit is biased between the first input voltage and a shifted ground voltage. The third elevator circuit is biased between the second input voltage and a ground voltage. The second and fourth elevator circuits are biased between the output voltage and an elevated ground voltage.

公开(公告)号：US20210193221A1

公开(公告)日：2021-06-24

申请号：US17129016

申请日：2020-12-21

Applicant: StMicroelectronics International N.V.

Inventor： Maurizio Francesco Perroni ,  Fabio Enrico Carlo Disegni ,  Massimo Caruso ,  Cesare Torti

IPC: G11C13/00

Abstract: An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.

公开(公告)号：US20250111878A1

公开(公告)日：2025-04-03

申请号：US18883201

申请日：2024-09-12

Applicant: STMicroelectronics International N.V.

Inventor： Fabio Enrico Carlo Disegni ,  Cesare Torti ,  Davide Manfré ,  Massimo Caruso ,  Maurizio Francesco Perroni

IPC: G11C16/08 ,  G11C16/10 ,  G11C16/28

Abstract: A row decoder circuit includes an input node receiving a row selection signal and an output node coupled to a memory device word line. A pull-down circuit couples the word line to ground in response to the row selection signal being asserted. A pull-up circuit couples the word line to a supply node in response to a deselection signal being de-asserted. An inverter circuit receives as input a control signal from a control node and produces the deselection signal. A current generator sources a biasing current to the control node. A further pull-down circuit couples the control node to ground in response to the row selection signal being asserted, and comprises a first cascode n-channel transistor, a cascode p-channel transistor, a second cascode n-channel transistor, and at least one selection transistor controlled by the row selection signal, all having their conductive channels arranged in series.

公开(公告)号：US20250078926A1

公开(公告)日：2025-03-06

申请号：US18817969

申请日：2024-08-28

Applicant: STMicroelectronics International N.V.

Inventor： Davide Manfré ,  Maurizio Francesco Perroni ,  Massimo Caruso ,  Fabio Enrico Carlo Disegni ,  Cesare Torti

IPC: G11C13/00

Abstract: A non-volatile memory includes a row decoder comprising, for each word-line, a respective pull-up connected to a first supply voltage and a switching circuit for selectively connecting one of the word-lines to ground. The row decoder comprises a demultiplexer connected to a second supply voltage smaller than the first, and configured to assert an enable signal as a function of an address signal. The switching circuit comprises two n-channel FETs connected in series between the word-line and ground, with the gate terminal of one FET connected to a first signal and the gate terminal of the other FET connected to a second voltage. A bias circuit is configured to set the voltage between the two FETs to the second voltage when the FETs are opened. The switching circuit comprises a p-channel FET connected between the word-line and the second voltage, and a gate terminal connected to a second signal.

公开(公告)号：US11380393B2

公开(公告)日：2022-07-05

申请号：US17129016

申请日：2020-12-21

Applicant: STMicroelectronics International N.V.

Inventor： Maurizio Francesco Perroni ,  Fabio Enrico Carlo Disegni ,  Massimo Caruso ,  Cesare Torti

IPC: G11C11/00 ,  G11C13/00

Abstract: An embodiment non-volatile memory device includes an array of memory cells arranged in rows and columns; a plurality of local bitlines; and a plurality of main bitlines, each main bitline being coupleable to a corresponding subset of local bitlines. The memory cells of each column are coupled to a corresponding local bitline. The memory device further includes a column decoder, which can be controlled electronically so as to couple each main bitline to a selected local bitline of the corresponding subset of local bitlines. The column decoder couples each main bitline to two different points of the corresponding selected local bitline.